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參數(shù)資料
型號： AD9117-DPG2-EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 31/52頁
文件大?。?/td> 0K
描述： IC DAC DUAL 14BIT LO PWR 40LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC®
DAC 的數(shù)量： 2
位數(shù)： 14
采樣率（每秒）： 125M
數(shù)據(jù)接口： 串行
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： AD9117
Data Sheet
AD9114/AD9115/AD9116/AD9117
Rev. C | Page 37 of 52
Register
Address
Bit
Name
Description
IRSET
0x04
7
IRSETEN
0 (default): IRSET resistor value for I channel is set by an external resistor connected
to the FADJI/AUXI pin. Nominal value for this external resistor is 4 k.
1: enables the on-chip IRSET value to be changed for I channel.
5:0
IRSET[5:0]
Changes the value of the on-chip IRSET resistor; this scales the full-scale current of
the DAC in ~0.25 dB steps twos complement (nonlinear), see Figure 98.
000000 (default): IRSET = 2 k.
011111: IRSET = 8 k.
100000: IRSET = 1.6 k.
111111: IRSET = 2 k.
IRCML
0x05
7
IRCMLEN
0 (default): IRCML resistor value for the I channel is set by an external resistor
connected to CMLI pin. Recommended value for this external resistor is 0 .
1: enables on-chip IRCML adjustment for I channel.
5:0
IRCML[5:0]
Changes the value of the on-chip IRCML resistor for I channel; this adjusts the
common-mode level of the DAC output stage.
000000 (default): IRCML = 60 .
100000: IRCML = 160 .
111111: IRCML = 260 .
Q DAC Gain
0x06
5:0
Q DACGAIN[5:0]
DAC Q fine gain adjustment; alters the full-scale current, as shown in Figure 99.
Default QDACGAIN = 0x00.
QRSET
0x07
7
QRSETEN
0 (default): QRSET resistor value for Q channel is set by an external resistor
connected to FADJI/AUXI pin. Nominal value for this external resistor is 4 k.
1: enables on-chip QRSET adjustment for Q channel.
5:0
QRSET[5:0]
Changes the value of the on-chip QRSET resistor; this scales the full-scale current of
the DAC in ~0.25 dB steps twos complement (nonlinear).
000000 (default): QRSET = 2 k.
011111: QRSET = 8 k.
100000: QRSET = 1.6 k.
111111: QRSET = 2 k.
QRCML
0x08
7
QRCMLEN
0 (default): QRCML resistor value for the Q channel is set by an external resistor
connected to CMLQ pin. Recommended value for this external resistor is 0 .
1: enables on-chip QRCML adjustment.
5:0
QRCML[5:0]
Changes the value of the on-chip QRCML resistor for Q channel; this adjusts the
common-mode level of the DAC output stage.
000000 (default): QRCML = 60 .
100000: QRCML = 160 .
111111: QRCML = 260 .
AUXDAC Q
0x09
7:0
QAUXDAC[7:0]
AUXDAC Q output voltage adjustment word LSBs.
0x3FF: sets AUXDAC Q output to full scale.
0x200: sets AUXDAC Q output to midscale.
0x000 (default): sets AUXDAC Q output to bottom of scale.
AUX CTLQ
0x0A
7
QAUXEN
0 (default): AUXDAC Q output disabled.
1: enables AUXDAC Q output.
6:5
QAUXRNG[1:0]
00 (default): sets AUXDAC Q output voltage range to 2 V.
01: sets AUXDAC Q output voltage range to 1.5 V.
10: sets AUXDAC Q output voltage range to 1.0 V.
11: sets AUXDAC Q output voltage range to 0.5 V.
4:2
QAUXOFS[2:0]
000 (default): sets AUXDAC Q top of range to 1.0 V.
001: sets AUXDAC Q top of range to 1.5 V.
010: sets AUXDAC Q top of range to 2.0 V.
011: sets AUXDAC Q top of range to 2.5 V.
100: sets AUXDAC Q top of range to 2.9 V.
1:0
QAUXDAC[9:8]
AUXDAC Q output voltage adjustment word MSBs (default = 00).
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