參數(shù)資料
型號(hào): AD9204BCPZRL7-40
廠商: Analog Devices Inc
文件頁(yè)數(shù): 15/36頁(yè)
文件大?。?/td> 0K
描述: IC ADC 10BIT 40MSPS 64LFCSP
標(biāo)準(zhǔn)包裝: 750
位數(shù): 10
采樣率(每秒): 40M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 97.7mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個(gè)單端,單極;2 個(gè)差分,單極
AD9204
Rev. 0 | Page 22 of 36
VOLTAGE REFERENCE
A stable and accurate 1.0 V voltage reference is built into the
AD9204. The VREF can be configured using either the internal
1.0 V reference or an externally applied 1.0 V reference voltage.
The various reference modes are summarized in the sections that
follow. The Reference Decoupling section describes the best
practices PCB layout of the reference.
Internal Reference Connection
A comparator within the AD9204 detects the potential at the
SENSE pin and configures the reference into two possible
modes, which are summarized in Table 10. If SENSE is grounded,
the reference amplifier switch is connected to the internal resistor
divider (see Figure 46), setting VREF to 1.0 V.
VREF
SENSE
0.5V
ADC
SELECT
LOGIC
0.1F
1.0F
VIN–A/VIN–B
VIN+A/VIN+B
ADC
CORE
08
12
2-
0
12
Figure 46. Internal Reference Configuration
In either internal or external reference mode, the maximum
input range of the ADC can be varied by configuring SPI
Address 0x18 as shown in Table 11, resulting in a selectable
differential span from 1 V p-p to 2 V p-p.
If the internal reference of the AD9204 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 47 shows
how the internal reference voltage is affected by loading.
0
–3.0
02
LOAD CURRENT (mA)
RE
F
E
RE
NCE
V
O
L
T
AG
E
RR
O
R
(
%
)
.0
–0.5
–1.0
–1.5
–2.0
–2.5
0.2
0.4
0.6
0.8
1.0
1.4
1.6
1.8
1.2
0
812
2-
0
14
INTERNAL VREF = 0.993V
Figure 47. VREF Accuracy vs. Load Current
Table 10. Reference Configuration Summary
Selected Mode
SENSE Voltage (V)
Resulting VREF (V)
Resulting Differential Span (V p-p)
Fixed Internal Reference
AGND to 0.2
1.0 internal
2.0
Fixed External Reference
AVDD
1.0 applied to external VREF pin
2.0
Table 11. Scaled Differential Span Summary
Selected Mode
Resulting VREF (V)
SPI Register 0x18 (Hex)
Resulting Differential Span (V p-p)
Fixed Internal or External Reference
1.0 (internal or external)
0xC0
1.0
Fixed Internal or External Reference
1.0 (internal or external)
0xC8
1.14
Fixed Internal or External Reference
1.0 (internal or external)
0xD0
1.33
Fixed Internal or External Reference
1.0 (internal or external)
0xD8
1.6
Fixed Internal or External Reference
1.0 (internal or external)
0xE0
2.0
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