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參數(shù)資料
| 型號(hào)： | AD9204BCPZRL7-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 80MSPS 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 150mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個(gè)單端，單極；2 個(gè)差分，單極 |
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AD9204
Rev. 0 | Page 34 of 36
Addr
(Hex)
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Comments
0x1C
B14
B13
B12
B11
B10
B9
B8
0x00
User-defined
pattern, 2 MSB
0x24
Open
B0
0x00
Least significant
byte of MISR; read
only
0x2A
Open
OR
output
enable
(local)
0x01
Disables the OR
pin for the
indexed channel
0x2E
Output assign
Open
0 = ADC A
1 = ADC B
(local)
Ch A =
0x00
Ch B =
0x01
Assign an ADC to
an output
channel
Digital Feature Control
0x10
0
Sync control
(global)
Open
Clock
divider
next sync
only
Clock
divider
sync
enable
Master
sync
enable
0x01
0x10
1
USR2
Enable
OEB
Pin 47
(local)
Open
Enable
GCLK
detect
Run
GCLK
Open
Disable
SDIO
pull-
down
0x88
Enables internal
oscillator for clock
rates < 5 MHz
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
Sync Control (Register 0x100)
Bits[7:3]—Reserved
Bit 2—Clock Divider Next Sync Only
If the master sync enable bit (Address 0x100, Bit 0) and the
clock divider sync enable bit (Address 0x100, Bit 1) are high,
Bit 2 allows the clock divider to sync to the first sync pulse it
receives and to ignore the rest. The clock divider sync enable
bit (Address 0x100, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal
is enabled when Bit 1 and Bit 0 are high and the device is
operating in continuous sync mode as long as Bit 2 of the
sync control is low.
Bit 0—Master Sync Enable
Bit 0 must be high to enable any of the sync functions.
USR2 (Register 0x101)
Bit 7—Enable OEB Pin 47
Normally set high, this bit allows Pin 47 to function as the
output enable. If it is set low, it disables Pin 47.
Bit 3—Enable GCLK Detect
Normally set high, this bit enables a circuit that detects encode
rates below about 5 MSPS. When a low encode rate is detected,
an internal oscillator, GCLK, is enabled, ensuring the proper
operation of several circuits. If set low, the detector is disabled.
Bit 2—Run GCLK
This bit enables the GCLK oscillator. For some applications
with encode rates below 10 MSPS, it may be preferable to set
this bit high to supersede the GCLK detector.
Bit 0—Disable SDIO Pull-Down
This bit can be set high to disable the internal 30 kΩ pull-down
on the SDIO pin, which can be used to limit the loading when
many devices are connected to the SPI bus.
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