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參數資料
| 型號： | AD9212ABCPZRL7-40 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 32/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT SRL 40MSPS 64LFCSP |
| 標準包裝： | 750 |
| 位數： | 10 |
| 采樣率（每秒）： | 40M |
| 數據接口： | 串行，SPI? |
| 轉換器數目： | 8 |
| 功率耗散（最大）： | 560mW |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 16 個單端，單極；8 個差分，單極 |
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AD9212
Data Sheet
Rev. E | Page 38 of 56
DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
The following is a list of the default and optional settings or
modes allowed on the AD9212 Rev. A evaluation board.
Power: Connect the switching power supply that is
provided with the evaluation kit between a rated 100 V ac
to 240 V ac wall outlet at 47 Hz to 63 Hz and P701.
AIN: The evaluation board is set up for a transformer-
coupled analog input with an optimum 50 Ω impedance
match of 150 MHz of bandwidth (see Figure 71). For more
bandwidth response, the differential capacitor across the
analog inputs can be changed or removed. The common
mode of the analog inputs is developed from the center
tap of the transformer or AVDD_DUT/2.
–14
–13
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
50
100
150
200
250
300
350
400
450
500
FREQUENCY (MHz)
AM
P
L
IT
UD
E
(
d
BF
S
)
–3dB CUTOFF = 186MHz
059
68
-08
6
Figure 71. Evaluation Board Full-Power Bandwidth
VREF: VREF is set to 1.0 V by tying the SENSE pin to
ground, R317. This causes the ADC to operate in 2.0 V p-p
full-scale range. A separate external reference option using
the ADR510 is also included on the evaluation
board.
Populate R312 and R313, and remove C307. Proper
use of
the VREF options is noted in the Voltage Reference
section.
RBIAS: RBIAS has a default setting of 10 kΩ (R301) to
ground and is used to set the ADC core bias current.
Clock: The default clock input circuitry is derived from a
simple transformer-coupled circuit using a high bandwidth
1:1 impedance ratio transformer (T401) that adds a very
low amount of jitter to the clock path. The clock input is
50 Ω terminated and ac-coupled to handle single-ended
sine wave types of inputs. The transformer converts the
single-ended input to a differential signal that is clipped
before entering the ADC clock inputs.
A differential LVPECL clock can also be used to clock the
ADC input using the AD9515 (U401). Populate R406 and
R407 with 0 Ω resistors, and remove R215 and R216 to
disconnect the default clock path inputs. In addition, populate
C205 and C206 with a 0.1 μF capacitor, and remove C409 and
C410 to disconnect the default clock path outputs. The
AD9515 has many pin-strappable options that are set to a
default mode of operation. Consult the AD9515 data sheet
for more information about these and other options.
In addition, an on-board oscillator is available on the OSC401
and can act as the primary clock source. The setup is quick
and involves installing R403 with a 0 Ω resistor and setting
the enable jumper (J401) to the on position. If the user wishes
to employ a different oscillator, two oscillator footprint options
are available (OSC401) to check the ADC performance.
PDWN: To enable the power-down feature, short J301 to
the on position (AVDD) for the PDWN pin.
SCLK/DTP: To enable the digital test pattern on the digital
outputs of the ADC, use J304. If J304 is tied to AVDD during
device power-up, Test Pattern 10 0000 0000 is enabled. See the
SCLK/DTP Pin section for details.
SDIO/ODM: To enable the low power, reduced signal option
(similar to the IEEE 1595.3 reduced range link LVDS output
standard), use J303. If J303 is tied to AVDD during device
power-up, it enables the LVDS outputs in a low power,
reduced signal option from the default ANSI-644 standard.
This option changes the signal swing from 350 mV p-p to
200 mV p-p, reducing the power of the DRVDD supply. See
the SDIO/ODM Pin section for more details.
CSB: To enable processing of the SPI information on the
SDIO and SCLK pins, tie J302 low in the always enable
mode. To ignore the SDIO and SCLK information, tie J302
to AVDD.
Non-SPI Mode: For users who wish to operate the DUT
without using the SPI, simply remove Jumpers J302, J303,
and J304. This disconnects the CSB, SCLK/DTP, and
SDIO/ODM pins from the control bus, allowing the DUT
to operate in its simplest mode. Each of these pins has
internal termination and will float to its respective level.
D + x, D x: If an alternative data capture method to the
setup shown in Figure 74 is used, optional receiver
terminations, R318 and R320 to R328, can be installed next
to the high speed backplane connector.
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相關代理商/技術參數 |
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| AD9212ABCPZRL7-65 | 功能描述:IC ADC 10BIT SRL 65MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
| AD9212BCPZ-40 | 制造商:Analog Devices 功能描述:ADC Octal Pipelined 40Msps 10-bit Serial 64-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10BIT ADC 40/65MSPS 1.8V SMD 制造商:Analog Devices 功能描述:IC, 10BIT ADC, 40/65MSPS, 1.8V, SMD |
| AD9212BCPZ-65 | 制造商:Analog Devices 功能描述:ADC Octal Pipelined 65Msps 10-bit Serial 64-Pin LFCSP EP |
| AD9212BCPZRL7-40 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9212BCPZRL7-65 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
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