參數(shù)資料
型號(hào): AD9215BRU-105
廠商: Analog Devices Inc
文件頁數(shù): 11/36頁
文件大?。?/td> 0K
描述: IC ADC 10BIT 105MSPS 3V 28-TSSOP
產(chǎn)品變化通告: Product Discontinuance 27/Oct/2011
設(shè)計(jì)資源: Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003)
Interfacing the High Frequency AD8331 to AD9215 (CN0096)
標(biāo)準(zhǔn)包裝: 50
位數(shù): 10
采樣率(每秒): 105M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 120mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 管件
輸入數(shù)目和類型: 2 個(gè)單端,單極;1 個(gè)差分,單極
配用: AD9215BCP-80EBZ-ND - BOARD EVAL FOR AD9215BCP-80
AD9215BCP-65EBZ-ND - BOARD EVAL FOR AD9215BCP-65
AD9215BCP-105EBZ-ND - BOARD EVAL FOR AD9215BCP-105
Data Sheet
AD9215
Rev. B | Page 19 of 36
02874-A-039
29
1
2
3
4
5
6
P13
P14
XFRIN1
OPTIONAL
XFR
T2
FT
C1–1–13
NC
CT
1
T1
ADT1–1WT
6
2
3
4
5
1
2
3
4
5
R
SINGLE
ENDED
R18
25
R3,
R17,
R18
ONLY
ONE
SHOULD
BE
ON
BOARD
AT
A
TIME
EXTREF
1V
MAX
E1
R1
10k
R9
10k
0.1
F
C12
C9
0.10
F
GND
AVDD
C29
10
F
C11
0.1
F
C7
0.1
F
GND
AV
DD
P7
A
B
C
D
P9
P8
P11
P10
E
C13
0.10
F
C22
10
F
P6
P1
P3
P4
1
2
3
4
GND
C8
0.1
F
P5
2
MODE
25
26
27
28
30
31
32
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
REFB
REFT
AGND
VIN+
AGND
AVDD
VIN–
AD9215
U4
VREF
SENSE
MODE
D9
OR
D8
D7
D6
DRVDD
DGND
D5
D3
D4
D2
D1
D0
16
15
14
13
12
11
10
9
DNC
CLK
DNC
PDWN
(LSB)
DRVDD
GND
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
ORX
D13X
D12X
D10X
D11X
D9X
D8X
D7X
D6X
D5X
D4X
D2X
D3X
D1X
D0X
(MSB)
OVERRANGE
BIT
AVDD
GND
DRVDD
VDL
GND
VAMP
P2
GND
H1
MTHOLE6
H2
MTHOLE6
H3
MTHOLE6
H4
MTHOLE6
3.0V
2.5V
5.0V
RP2
220
RP1
220
SENSE
PIN
SOLDERABLE
JUMPER:
E
TO
A:
EXTERNAL
VOLTAGE
DIVIDER
E
TO
B:
INTERNAL
1V
REFERENCE
(DEFAULT)
E
TO
C:
EXTERNAL
REFERENCE
E
TO
D:
INTERNAL
0.5V
REFERENCE
MODE
PIN
SOLDERABLE
JUMPER:
5
TO
1:
TWOS
COMPLEMENT/DCS
OFF
5
TO
2:
TWOS
COMPLEMENT/DCS
ON
5
TO
3:
OFFSET
BINARY/DCS
ON
5
TO
4:
OFFSET
BINARY/DCS
OFF
GND
R8
1k
CLK
AVDD
GND
R25
1k
R13
1k
R15
33
AVDD
GND
C19
10pF
OR
L1
FOR
FILTER
GND
AVDD
R4
33
R36
1k
R26
1k
GND
AV
DD
AVDD
GND
VIN+
VIN–
C21
SELECT
C23
SELECT
R2
XX
R10
36
R12
0
AMPIN
X
OUT
GND
X
OUT
B
R3
0
R11
36
C5
0.1
F
C26
10pF
E
45
C16
0.1
F
R42
0
C6
0.1
F
GND
AMP
AMPINB
C15
0.1
F
L1
100
GND
PRI
SEC
PRI
SEC
GND
C18
0.10
F
X
FRIN
X
OUT
B
CT
X
OUT
J1
R5
1k
R7
1k
R6
1k
Figure 41. LFCSP Evaluation Board Schematic, Analog Inputs and DUT
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