參數(shù)資料
型號(hào)： AD9216-80PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 16/40頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9216 80MSPS
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 2
位數(shù)： 10
采樣率（每秒）： 80M
數(shù)據(jù)接口： 并聯(lián)
輸入范圍： 2 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 234mW @ 80MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9216-80
已供物品： 板
相關(guān)產(chǎn)品： AD9216BCPZRL7-105-ND - IC ADC 10BIT DL 105MSPS 64-LFCSP
AD9216BCPZ-105-ND - IC ADC 10BIT DL 105MSPS 64LFCSP
AD9216BCPZ-80-ND - IC ADC 10BIT DUAL 80MSPS 64LFCSP
AD9216BCPZRL7-80-ND - IC ADC 10BIT DUAL 80MSPS 64LFCSP
AD9216
Rev. A | Page 23 of 40
OUTPUT CODING
Table 8.
Code
(VIN+) (VIN)
Offset Binary
Twos Complement
1023
> +0.998 V
11 1111 1111
01 1111 1111
1023
+0.998 V
11 1111 1111
01 1111 1111
1022
+0.996 V
11 1111 1110
01 1111 1110
513
+0.002 V
10 0000 0001
00 0000 0001
512
+0.0 V
10 0000 0000
00 0000 0000
511
0.002 V
01 1111 1111
11 1111 1111
1
0.998 V
00 0000 0001
10 0000 0001
0
1.000 V
00 0000 0000
10 0000 0000
0
< 1.000 V
00 0000 0000
10 0000 0000
TIMING
The AD9216 provides latched data outputs with a pipeline delay
of six clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal. Refer to
Figure 2 for a detailed timing diagram.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9216.
These transients can detract from the converter’s dynamic
performance. The lowest conversion rate of the AD9216 is
10 MSPS. At clock rates below 10 MSPS, dynamic perform-
ance may degrade.
DATA FORMAT
The AD9216 data output format can be configured for either
twos complement or offset binary. This is controlled by the
data format select pin (DFS). Connecting DFS to AGND
produces offset binary output data. Conversely, connecting
DFS to AVDD formats the output data as twos complement.
The output data from the dual ADCs can be multiplexed onto a
single, 10-bit output bus. The multiplexing is accomplished by
toggling the MUX_SELECT bit, which directs channel data to
the same or opposite channel data port. When MUX_SELECT
is logic high, the Channel A data is directed to the Channel A
output bus, and the Channel B data is directed to the Channel B
output bus. When MUX_SELECT is logic low, the channel
data is reversed; that is, the Channel A data is directed to the
Channel B output bus, and the Channel B data is directed to
the Channel A output bus. By toggling the MUX_SELECT bit,
multiplexed data is available on either of the output data ports.
If the ADCs are run with synchronized timing, this same clock
can be applied to the MUX_SELECT pin. Any skew between
CLK_A, CLK_B, and MUX_SELECT can degrade ac perform-
ance. It is recommended to keep the clock skew < 100 pHs.
After the MUX_SELECT rising edge, either data port has
the data for its respective channel; after the falling edge, the
alternate channel’s data is placed on the bus. Typically, the
other unused bus is disabled by setting the appropriate OEB
high to reduce power consumption and noise. Figure 46 shows
an example of multiplex mode. When multiplexing data, the
data rate is two times the sample rate. Note that both channels
must remain active in this mode and that each channel’s power-
down pin must remain low.
B–7
A–6
B–6
A–5
B–5
A–4
B–4
A–3
B–3
A–2
B–2
A–1
B–1
A0
B0
A1
B1
A–1
A0
A1
A2
A3
A4
A5
A6
A7
A8
B–1
B0
B1
B2
B3
B4
B5
B6
B7
B8
ANALOG INPUT
ADC A
ANALOG INPUT
ADC B
CLK_A = CLK_B =
MUX_SELECT
D0_A
–D11_A
04775-013
Figure 46. Example of Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9216BCP-105 制造商:Analog Devices 功能描述:ADC DUAL PIPELINED 105MSPS 10-BIT PARALLEL 64LFCSP EP - Bulk
AD9216BCP-65 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 65/80/105 MSPS Dual A/D Converter
AD9216BCPZ-105 功能描述:IC ADC 10BIT DL 105MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極
AD9216BCPZ-65 功能描述:IC ADC 10BIT DUAL 65MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6
AD9216BCPZ-80 功能描述:IC ADC 10BIT DUAL 80MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極
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