AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; A
參數(shù)資料
型號: AD9216-80PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 37/40頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9216 80MSPS
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 2
位數(shù): 10
采樣率(每秒): 80M
數(shù)據(jù)接口: 并聯(lián)
輸入范圍: 2 Vpp
在以下條件下的電源(標(biāo)準(zhǔn)): 234mW @ 80MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9216-80
已供物品:
相關(guān)產(chǎn)品: AD9216BCPZRL7-105-ND - IC ADC 10BIT DL 105MSPS 64-LFCSP
AD9216BCPZ-105-ND - IC ADC 10BIT DL 105MSPS 64LFCSP
AD9216BCPZ-80-ND - IC ADC 10BIT DUAL 80MSPS 64LFCSP
AD9216BCPZRL7-80-ND - IC ADC 10BIT DUAL 80MSPS 64LFCSP
AD9216
Rev. A | Page 6 of 40
SWITCHING SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = 0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 4.
AD9216BCPZ-65
AD9216BCPZ-80
AD9216BCPZ-105
Parameter
Temp
Test Level
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
SWITCHING PERFORMANCE
Maximum Conversion Rate
Full
VI
65
80
105
MSPS
Minimum Conversion Rate
Full
IV
10
MSPS
CLK Period
Full
VI
15.4
12.5
9.5
nS
CLK Pulse Width High
Full
VI
4.6
4.4
3.8
nS
CLK Pulse Width Low
Full
VI
4.6
4.4
3.8
nS
OUTPUT PARAMETERS1
Output Propagation Delay2 (tPD)
25°C
I
4.5
6.4
4.5
6.4
4.5
6.4
nS
Valid Time3 (tV)
25°C
I
2.0
Output Rise Time (10% to 90%)
25°C
V
1.0
nS
Output Fall Time (10% to 90%)
25°C
V
1.0
nS
Output Enable Time4
Full
IV
1
Cycle
Output Disable Time4
Full
IV
1
Cycle
Pipeline Delay (Latency)
Full
IV
6
Cycle
APERTURE
Aperture Delay (tA)
25°C
V
1.5
nS
Aperture Uncertainty (tJ)
25°C
V
0.5
pS rms
Wake-Up Time5
25°C
V
7
ms
OUT-OF-RANGE RECOVERY TIME
25°C
V
1
Cycle
1 CLOAD equals 5 pF maximum for all output switching parameters.
2 Output delay is measured from clock 50% transition to data 50% transition.
3 Valid time is approximately equal to the minimum output propagation delay.
4 Output enable time is OEB_A, OEB_B falling to respective channel outputs coming out of high impedance. Output disable time is OEB_A, OEB_B rising to respective
channel outputs going into high impedance.
5 Wake-up time is dependent on value of decoupling capacitors; typical values shown for 0.1 F and 10 F capacitors on REFT and REFB.
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參數(shù)描述
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