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參數(shù)資料
| 型號(hào)： | AD9218BST-105 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT DUAL 105MSPS 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 105M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 565mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個(gè)差分，單極 |
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AD9218
Rev. C | Page 10 of 28
TERMINOLOGY
Full-Scale Input Power
Analog Bandwidth
Expressed in dbm. Computed using the following equation:
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
=
001
.
0
log
10
2
INPUT
Scale
Full
Scale
Full
Z
rms
V
Power
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Gain Error
Gain error is the difference between the measured and the ideal
full-scale input voltage range of the ADC.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Crosstalk
Coupling onto one channel being driven by a low level signal
(–40 dBFS) when the adjacent interfering channel is driven by a
full-scale signal.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Differential Analog Input Resistance,
Differential Analog Input Capacitance,
Differential Analog Input Impedance
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least-square curve fit.
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180
degrees out of phase. Peak-to-peak differential is computed by
rotating the input phase 180 degrees and again taking the peak
measurement. The difference is then computed between both
peak measurements.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between the 50% level crossing of ENCODE A or
ENCODE B and the 50% level crossing of the respective
channel’s output data bit.
Noise (for Any Range Within the ADC)
Differential Nonlinearity
×
=
10
001
.
0
dBFS
dBc
dBm
NOISE
Signal
SNR
FS
Z
V
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB)
where Z is the input impedance, FS is the full scale of the device
for the frequency in question, SNR is the value for the particular
input level, and Signal is the signal level within the ADC
reported in dB below full scale. This value includes both
thermal and quantization noise.
The effective number of bits is calculated from the measured
SNR based on the equation
02
.
6
76
.
1
dB
=
MEASURED
SNR
ENOB
Power Supply Rejection Ratio
ENCODE Pulse Width/Duty Cycle
The ratio of a change in input offset voltage to a change in
power supply voltage.
Pulse width high is the minimum amount of time that the
ENCODE pulse should be left in Logic 1 state to achieve rated
performance; pulse width low is the minimum time ENCODE
pulse should be left in low state. See timing implications of
changing tENCH in text. At a given clock rate, these specifications
define an acceptable ENCODE duty cycle.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9218BST-40 | 制造商:Analog Devices 功能描述:ADC Dual Pipelined 40Msps 10-bit Parallel 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:DUAL 10 BIT 105/80/65/40 MSPS ADC - Bulk 制造商:Analog Devices 功能描述:SEMICONDUCTOR ((NW)) |
| AD9218BST-65 | 制造商:Analog Devices 功能描述:ADC Dual Pipelined 65Msps 10-bit Parallel 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:DUAL 10 BIT 105/80/65 MSPS ADC - Bulk 制造商:Analog Devices 功能描述:IC 10-BIT ADC |
| AD9218BST-80 | 制造商:Analog Devices 功能描述:ADC Dual Pipelined 80Msps 10-bit Parallel 48-Pin LQFP 制造商:Analog Devices 功能描述:IC 10-BIT ADC |
| AD9218BST-RL105 | 功能描述:IC ADC 10BIT DUAL 105MSPS 48LQFP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD9218BST-RL40 | 制造商:Analog Devices 功能描述:ADC Dual Pipelined 40Msps 10-bit Parallel 48-Pin LQFP T/R |
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