參數(shù)資料
型號(hào): AD9218BST-105
廠商: Analog Devices Inc
文件頁(yè)數(shù): 28/28頁(yè)
文件大小: 0K
描述: IC ADC 10BIT DUAL 105MSPS 48LQFP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 10
采樣率(每秒): 105M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 565mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 托盤(pán)
輸入數(shù)目和類(lèi)型: 2 個(gè)差分,單極
AD9218
Rev. C | Page 9 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
0
20
01
-00
5
GND
V
D
EN
C
A
V
DD
GN
D
D9
A
(M
SB
)
D8
A
D7
A
D6
A
D5
A
D4
A
D3
A
D2
A
V
D
EN
C
B
V
DD
GN
D
(M
SB
)D
9
B
D8
B
D7
B
D6
B
D5
B
D4
B
D3
B
D2
B
S1
S2
GND
AINA
DFS/GAIN
AINB
REFINA
REFINB
D1A
GND
VDD
D1B
D0A
GND
D0B
GND
VD
REFOUT
VD
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
AD9218
TOP VIEW
(Not to Scale)
Figure 5. Pin Configuration
Table 7. Pin Function Descriptions
Pin Number
Mnemonic
Description
GND
Ground.
1, 12, 16, 27, 29,
32, 34, 45
2
AINA
Analog Input for Channel A.
A
IN
3
Analog Input for Channel A (Complementary).
4
DFS/GAIN
Data Format Select and Analog Input Gain Mode. Low = offset binary output available, 1 V p-p supported;
high = twos complement output available, 1 V p-p supported; floating = offset binary output available,
2 V p-p supported; set to V
= twos complement output available, 2 V p-p supported.
REF
5
REFINA
Reference Voltage Input for Channel A.
6
REFOUT
Internal Reference Voltage.
7
REFINB
Reference Voltage Input for Channel B.
8
S1
User Select No. 1. See Table 6.
9
S2
User Select No. 2. See Table 6.
10
B
A
IN
Analog Input for Channel B (Complementary).
11
AINB
Analog Input for Channel B.
13, 30, 31, 48
VD
Analog Supply (3 V).
14
ENCB
Clock Input for Channel B.
15, 28, 33, 46
VDD
Digital Supply (2.5 V to 3.6 V).
17 to 26
D9 to D0
B
Digital Output for Channel B (D9 = MSB).
B
35 to 44
D0A to D9A
Digital Output for Channel A (D9A = MSB).
47
ENCA
Clock Input for Channel A.
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