參數(shù)資料
型號： AD9222-65EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 17/60頁
文件大小： 0K
描述： BOARD EVALUATION AD9222 65MSPS
設計資源： AD9212/22/52 Gerber Files
標準包裝： 1
ADC 的數(shù)量： 8
位數(shù)： 12
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行
輸入范圍： 2 Vpp
在以下條件下的電源（標準）： 910mW @ 65MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9222
已供物品： 板
AD9222
Data Sheet
Rev. F | Page 24 of 60
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9222 sample clock inputs
(CLK+ and CLK) should be clocked with a differential signal.
This signal is typically ac-coupled to the CLK+ and CLK pins
via a transformer or capacitors. These pins are biased internally
and require no additional biasing.
Figure 63 shows a preferred method for clocking the AD9222. The
low jitter clock source is converted from a single-ended signal
to a differential signal using an RF transformer. The back-to-
back Schottky diodes across the secondary transformer limit
clock excursions into the AD9222 to approximately 0.8 V p-p
differential. This helps prevent the large voltage swings of the
clock from feeding through to other portions of the AD9222,
and it preserves the fast rise and fall times of the signal, which
are critical to low jitter performance.
0.1F
SCHOTTKY
DIODES:
HSM2812
CLK+
50
100
CLK–
CLK+
ADC
AD9222
MINI-CIRCUITS
ADT1-1WT, 1:1Z
XFMR
05967-
050
Figure 63. Transformer-Coupled Differential Clock
Another option is to ac-couple a differential PECL signal to the
sample clock input pins as shown in Figure 64. The AD9510/
drivers offers excellent jitter performance.
CLK+
100
0.1F
240
240
CLK–
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
50
1
50
1
CLK
150
RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADC
AD9222
05967-
051
PECL DRIVER
Figure 64. Differential PECL Sample Clock
CLK+
CLK–
10
0
0.1F
501
LVDS DRIVER
501
CLK
1
50 RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADC
AD9222
05967-
052
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
Figure 65. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be directly driven from a CMOS gate, and the
CLK pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 k resistor (see Figure 66). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages of up to 3.3 V, making the
selection of the drive logic voltage very flexible.
CLK+
0.1F
39k
CMOS DRIVER
50
1
OPTIONAL
100
0.1F
CLK
1
50 RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
AD9222
05967-
053
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
Figure 66. Single-Ended 1.8 V CMOS Sample Clock
CLK+
0.1F
CMOS DRIVER
50
1
OPTIONAL
100
CLK
150
RESISTOR IS OPTIONAL.
0.1F
CLK–
CLK+
ADC
AD9222
05967-
054
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
Figure 67. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9222 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9222. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. However,
some applications may require the DCS function to be off. If so,
keep in mind that the dynamic range performance can be affected
when operated in this mode. See the Memory Map section for
more details on using this feature.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
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