參數(shù)資料
型號(hào): AD9222-65EBZ
廠商: Analog Devices Inc
文件頁數(shù): 21/60頁
文件大小: 0K
描述: BOARD EVALUATION AD9222 65MSPS
設(shè)計(jì)資源: AD9212/22/52 Gerber Files
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 8
位數(shù): 12
采樣率(每秒): 65M
數(shù)據(jù)接口: 串行
輸入范圍: 2 Vpp
在以下條件下的電源(標(biāo)準(zhǔn)): 910mW @ 65MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9222
已供物品:
AD9222
Data Sheet
Rev. F | Page 28 of 60
500
400
300
200
100
–500
–400
–300
–200
–100
0
–1.0ns
–1.5ns
–0.5ns
0ns
0.5ns
1.0ns
1.5ns
EYE
D
IA
G
R
A
M
VO
L
T
A
G
E
(m
V)
EYE: ALL BITS
ULS: 7591/15591
20
40
60
80
100
140
120
0
–300ps
–200ps
–100ps
0ps
100ps
200ps
300ps
TIE
J
ITTE
R
H
IS
TOGR
A
M
(
H
it
s
)
05967-
105
Figure 76. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4, AD9222-65
400
300
200
100
–400
–300
–200
–100
0
–0.5ns
0ns
0.5ns
EYE
D
IA
G
R
A
M
VO
L
T
A
G
E
(m
V)
EYE: ALL BITS
ULS: 12072/12072
80
50
10
20
30
40
60
70
0
–150ps
–100ps
–50ps
0ps
50ps
100ps
150ps
TIE
J
ITTE
R
H
IS
TOGR
A
M
(
H
it
s
)
–1.0ns
1.5ns
–1.5ns
1.0ns
05967-
060
Figure 77. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Termination
on and Trace Lengths Greater than 24 Inches on Standard FR-4, AD9222-50
500
400
300
200
100
–500
–400
–300
–200
–100
0
–1.0ns
–1.5ns
–0.5ns
0ns
0.5ns
1.0ns
1.5ns
EYE
D
IA
G
R
A
M
VO
L
T
A
G
E
(m
V)
EYE: ALL BITS
ULS: 8000/15600
20
40
60
80
100
140
120
0
–200ps
–100ps
0ps
100ps
200ps
300ps
TIE
J
ITTE
R
H
IS
TOGR
A
M
(
H
it
s
)
05967-
104
Figure 78. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Termination
on and Trace Lengths Greater than 24 Inches on Standard FR-4, AD9222-65
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 8.
To change the output data format to twos complement, see the
Memory Map section.
Table 8. Digital Output Coding
Code
(VIN + x) (VIN x),
Input Span = 2 V p-p (V)
Digital Output Offset Binary
(D11 ... D0)
4095
+1.00
1111 1111 1111
2048
0.00
1000 0000 0000
2047
0.000488
0111 1111 1111
0
1.00
0000 0000 0000
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 12 bits
times the sample clock rate, with a maximum of 780 Mbps
(12 bits × 65 MSPS = 780 Mbps). The lowest typical conversion
rate is 10 MSPS. However, if lower sample rates are required for
a specific application, the PLL can be set up via the SPI to allow
encode rates as low as 5 MSPS. See the Memory Map section to
enable this feature.
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