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參數(shù)資料
| 型號： | AD9224ARS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Complete 12-Bit 40 MSPS Monolithic A/D Converter |
| 中文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大小： | 309K |
| 代理商： | AD9224ARS |
–3–
REV. A
AD9224
AC SPECIFICATIONS
Parameter
Min
Typ
Max
Units
SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D)
f
INPUT
= 2.5 MHz
f
INPUT
= 10 MHz
SIGNAL-TO-NOISE RATIO (SNR)
f
INPUT
= 2.5 MHz
f
INPUT
= 10 MHz
TOTAL HARMONIC DISTORTION (THD)
f
INPUT
= 2.5 MHz
f
INPUT
= 10 MHz
SPURIOUS FREE DYNAMIC RANGE
f
INPUT
= 2.5 MHz
f
INPUT
= 10 MHz
Full Power Bandwidth
Small Signal Bandwidth
Aperture Delay
Aperture Jitter
65
63.5
68.3
68.0
dB
dB
65.3
64.6
69.1
68.4
dB
dB
–80
–78
–71
–67.4
dB
dB
71.1
67.9
81
79
120
120
1
4
dB
dB
MHz
MHz
ns
ps rms
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Parameters
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (V
IN
= DRVDD)
Low Level Input Current (V
IN
= 0 V)
Input Capacitance
LOGIC OUTPUTS (With DRVDD = 5 V)
High Level Output Voltage (I
OH
= 50
μ
A)
High Level Output Voltage (I
OH
= 0.5 mA)
Low Level Output Voltage (I
OL
= 1.6 mA)
Low Level Output Voltage (I
OL
= 50
μ
A)
Output Capacitance
LOGIC OUTPUTS (With DRVDD = 3 V)
High Level Output Voltage (I
OH
= 50
μ
A)
High Level Output Voltage (I
OH
= 0.5 mA)
Low Level Output Voltage (I
OL
= 1.6 mA)
Low Level Output Voltage (I
OL
= 50
μ
A)
Symbol
Min
Typ
Max
Units
V
IH
V
IL
I
IH
I
IL
C
IN
+3.5
V
V
μ
A
μ
A
pF
+1.0
+10
+10
–10
–10
5
V
OH
V
OH
V
OL
V
OL
C
OUT
+4.5
+2.4
V
V
V
V
pF
+0.4
+0.1
5
V
OH
V
OH
V
OL
V
OL
+2.95
+2.80
V
V
V
V
+0.4
+0.05
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
Parameters
Clock Period
1
CLOCK Pulsewidth High
2
CLOCK Pulsewidth Low
Output Delay
Pipeline Delay (Latency)
Symbol
t
C
t
CH
t
CL
t
OD
Min
25
12.37
12.37
13
Typ
Max
Units
ns
ns
ns
ns
Clock Cycles
3
NOTES
1
The clock period may be extended to 1 ms without degradation in specified performance @ +25
°
C.
2
For operation at 40 MHz, the clock must be held to 50% duty cycle. See section on clock shaping in text.
Specifications subject to change without notice.
(AVDD = +5 V, DRVDD = +3 V, f
SAMPLE
= 40 MSPS, VREF
= 2.0 V, T
MIN
to T
MAX
, Differential Input unless otherwise noted)
(AVDD = +5 V, DRVDD = +5 V, unless otherwise noted)
(T
MIN
to T
MAX
with AVDD = + 5 V, DRVDD = +5 V, C
L
= 20 pF)
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