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參數(shù)資料
| 型號： | AD9225-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 12-Bit, 25 MSPS Monolithic A/D Converter |
| 中文描述： | 完整的12位，25 MSPS的單片機的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 321K |
| 代理商： | AD9225-EB |
AD9225
–21–
REV. A
The digital activity on the AD9225 chip falls into two general
categories: correction logic, and output drivers. The internal
correction logic draws relatively small surges of current, mainly
during the clock transitions. The output drivers draw large
current impulses while the output bits are changing. The size
and duration of these currents are a function of the load on the
output bits: large capacitive loads are to be avoided. Note, the
internal correction logic of the AD9225 is referenced to AVDD
while the output drivers are referenced to DRVDD.
The decoupling shown in Figure 43, 0.1
μ
F ceramic chip capaci-
tors and a 10
μ
F tantalum are appropriate for a reasonable
capacitive load on the digital outputs (typically 20 pF on each
pin). Applications involving greater digital loads should consider
increasing the digital decoupling proportionally, and/or using
external buffers/latches.
0.1
m
F
DRVDD
DRVSS
AD9225
10
m
F
Figure 43. Digital Supply Decoupling
A complete decoupling scheme will also include large tantalum
or electrolytic capacitors on the PCB to reduce low frequency
ripple to negligible levels. Refer to the AD9225/AD9225EB
schematic and layouts in Figures 44–50 for more information
regarding the placement of decoupling capacitors.
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