參數(shù)資料
型號(hào)： AD9228
廠商： Analog Devices, Inc.
英文描述： Quad, 12-bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
中文描述： 四，12位，六十五分之四十○MSPS的串行LVDS 1.8弗吉尼亞州/ D轉(zhuǎn)換器
文件頁(yè)數(shù)： 22/52頁(yè)
文件大小： 1659K
代理商： AD9228
AD9228
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(f
A
) due only to aperture jitter (t
J
) can be calculated by
SNR degradation
= 20 × log 10 [1/2 × π ×
f
A
×
t
J
]
Rev. 0 | Page 22 of 52
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 55).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9228.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
Refer to the
AN-501 Application Note
and the
AN-756
Application Note
for more in-depth information about jitter
performance as it relates to ADCs (visit
www.analog.com
).
1
10
100
1000
0
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
90
100
110
120
130
0.125 ps
0.25 ps
0.5 ps
1.0 ps
2.0 ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
RMS CLOCK JITTER REQUIREMENT
S
Figure 55. Ideal SNR vs. Input Frequency and Jitter
Power Dissipation and Power-Down Mode
As shown in Figure 56 and Figure 57, the power dissipated by
the AD9228 is proportional to its sample rate. The digital power
dissipation does not vary much because it is determined primarily
by the DRVDD supply and bias current of the LVDS output drivers.
10
20
15
30
35
25
40
C
ENCODE (MSPS)
0
180
220
200
240
300
340
320
360
260
280
0
20
40
100
140
120
180
160
60
80
DRVDD CURRENT
TOTAL POWER
AVDD CURRENT
P
Figure 56. Supply Current vs. f
SAMPLE
for f
IN
= 10.3 MHz, f
SAMPLE
= 40 MSPS
10
20
30
40
50
60
C
P
ENCODE (MSPS)
0
0
50
100
150
200
250
300
340
320
360
380
400
420
440
460
480
DRVDD CURRENT
TOTAL POWER
AVDD CURRENT
Figure 57. Supply Current vs. f
SAMPLE
for f
IN
= 10.3 MHz, f
SAMPLE
= 65 MSPS
相關(guān)PDF資料
PDF描述
AD9228-65EB Quad, 12-bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
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AD9229BCP-65 Quad 12-Bit, 50/65 MSPS Serial LVDS 3V A/D Converter
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9228_07 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Quad, 12-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
AD9228-65EB 制造商:Analog Devices 功能描述:
AD9228-65EB1 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:High Speed ADC USB FIFO Evaluation Kit
AD9228-65EBZ 功能描述:BOARD EVAL FOR AD9228 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件
AD9228ABCPZ-40 功能描述:IC ADC 12BIT SPI/SRL 40M 48LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類(lèi)型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱(chēng):497-5435-6
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