參數(shù)資料
型號(hào)： AD9229ABCPZRL7-65
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/40頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT SRL 65MSPS 48LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 12
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 1.47W
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)差分，單極
AD9229
Rev. B | Page 19 of 40
An internal reference buffer creates the positive and negative
reference voltages, REFT and REFB, respectively, that defines
the span of the ADC core. The output common-mode of the
reference buffer is set to midsupply, and the REFT and REFB
voltages and span are defined as
REFT = 1/2 (AVDD + VREF)
REFB = 1/2 (AVDD VREF)
Span = 2 × (REFT REFB) = 2 × VREF
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage
and, by definition, the input span is twice the value of the
VREF voltage.
The internal voltage reference can be pin-strapped to fixed
values of 0.5 V or 1.0 V or adjusted within the same range, as
discussed in the Internal Reference Connection section.
Maximum SNR performance is achieved by setting the AD9229
to the largest input span of 2 V p-p.
The SHA should be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
levels are defined in Figure 35 and Figure 36.
Differential Input Configurations
Optimum performance is achieved by driving the AD9229 in a
differential input configuration. For ultrasound applications,
the AD8332 differential driver provides excellent performance
and a flexible interface to the ADC (see Figure 37).
AD8332
1.0k
Ω
1.0k
Ω
374
Ω
187
Ω
04418-032
AD9229
VIN+
VIN–
AVDD
AGND
R
C
0.1
μF
187nH
VREF
0.1
μF
0.1
μF
0.1
μF
0.1
μF10μF
0.1
μF
1V p-p
0.1
μF
AVDD
LNA
120nH
VGA
VOH
VIP
INH
22p
LMD
VIN
LOP
LON
VOL
18nF
274
Ω
Figure 37. Differential Input Configuration Using the AD8332
However, the noise performance of most amplifiers is not
adequate to achieve the true performance of the AD9229. For
applications where SNR is a key parameter, differential transfor-
mer coupling is the recommended input configuration. An
example of this is shown in Figure 38.
In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and may need to be reduced
or removed.
04418-033
AD9229
VIN+
VIN–
AVDD
AGND
2Vp-p
R
C
49.9
Ω
0.1
μF
1k
Ω
1k
Ω
AVDD
Figure 38. Differential Transformer—Coupled Configuration
Single-Ended Input Configuration
A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, SFDR and
distortion performance degrade due to the large input
common-mode swing. However, if the source impedances
on each input are matched, there should be little effect on
SNR performance. Figure 39 details a typical single-ended
input configuration.
04418-
034
2V p-p
R
C
49.9
Ω
0.1
μF
10
μF
10
μF
0.1
μF
AD9229
VIN+
VIN–
AVDD
AGND
AVDD
1k
Ω
1k
Ω
1k
Ω
1k
Ω
Figure 39. Single-Ended Input Configuration
CLOCK INPUT CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensi-
tive to clock duty cycle. Typically, a 10% tolerance is required on
the clock duty cycle to maintain dynamic performance charac-
teristics. The AD9229 has a self-contained clock duty cycle
stabilizer that retimes the nonsampling edge, providing an
internal clock signal with a nominal 50% duty cycle. This allows
a wide range of clock input duty cycles without affecting the
performance of the AD9229.
An on-board phase-locked loop (PLL) multiplies the input
clock rate for the purpose of shifting the serial data out. The
stability criteria for the PLL limits the minimum sample clock
rate of the ADC to 10 MSPS. Assuming steady state operation of
the input clock, any sudden change in the sampling rate could
create an out-of-lock condition leading to invalid outputs at the
DCO, FCO, and data out pins.
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