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參數(shù)資料
| 型號(hào)： | AD9233BCPZRL7-105 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 105MSPS 48-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 105M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 350mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；1 個(gè)差分，單極 |
| 配用： | AD9233-125EBZ-ND - BOARD EVALUATION FOR AD9233 |
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AD9233
Rev. A | Page 18 of 44
Table 9. Reference Configuration Summary
Selected Mode
SENSE Voltage
Resulting VREF (V)
Resulting Differential Span (V p-p)
External Reference
AVDD
N/A
2 × External Reference
Internal Fixed Reference
VREF
0.5
1.0
Programmable Reference
0.2 V to VREF
0.5 × (1 + R2/R1) (See Figure 43)
2 × VREF
Internal Fixed Reference
AGND to 0.2 V
1.0
2.0
0
–1.25
02
LOAD CURRENT (mA)
RE
F
E
RE
NCE
V
O
L
T
AG
E
RR
O
R
(
%
)
.0
–0.25
–0.50
–0.75
–1.00
0.5
1.0
1.5
VREF = 0.5V
VREF = 1V
0
549
2-
0
32
Figure 44. VREF Accuracy vs. Load
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift
characteristics. Figure 45 shows the typical drift characteristics
of the internal reference in both 1 V and 0.5 V modes.
–40
–20
10
0
TEMPERATURE (°C)
RE
F
E
RE
NC
E
V
O
L
T
AG
E
RRO
R
(
m
V
)
8
6
4
2
80
0
204060
VREF = 0.5V
VREF = 1V
05
49
2-
0
33
Figure 45. Typical VREF Drift
When the SENSE pin is tied to the AVDD pin, the internal
reference is disabled, allowing the use of an external reference.
An internal resistor divider loads the external reference with an
equivalent 6 kΩ load (see Figure 11). In addition, an internal
buffer generates the positive and negative full-scale references
for the ADC core. Therefore, the external reference must be
limited to a maximum of 1 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9233 sample clock inputs
(CLK+ and CLK) should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ pin and the
CLK pin via a transformer or capacitors. These pins are biased
internally (see Figure 5) and require no external bias.
Clock Input Options
The AD9233 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal used, the jitter of the clock
source is of the most concern, as described in the Jitter
Considerations section.
Figure 46 shows one preferred method for clocking the
AD9233. A low jitter clock source is converted from single-
ended to a differential signal using an RF transformer. The
back-to-back Schottky diodes across the transformer secondary
limit clock excursions into the AD9233 to approximately
0.8 V p-p differential. This helps prevent the large voltage
swings of the clock from feeding through to other portions of
the AD9233 while preserving the fast rise and fall times of the
signal, which are critical to a low jitter performance.
05
49
2-
0
48
0.1F
SCHOTTKY
DIODES:
HSMS2812
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
AD9233
MIN-CIRCUITS
ADT1–1WT, 1:1Z
XFMR
Figure 46. Transformer Coupled Differential Clock
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
excellent jitter performance.
CLOCK
INPUT
100
0.1F
240
CLOCK
INPUT
054
92-
049
PECL DRIVER
50*
50*
CLK
*50 RESISTORS ARE OPTIONAL
CLK–
CLK+
ADC
AD9233
AD951x
Figure 47. Differential PECL Sample Clock
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