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參數(shù)資料
| 型號： | AD9237BCPZRL7-65 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SGL 65MSPS 32LFCSP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標準包裝： | 1,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 功率耗散（最大）： | 190mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
AD9237
Data Sheet
Rev. B | Page 8 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
0
545
5-
00
3
NOTES
1. DNC = DO NOT CONNECT.
2. IT IS RECOMMENDED THAT THE EXPOSED PADDLE
BE SOLDERED TO THE GROUND PLANE.
MODE2
CLK
OE
PDWN
GC
DNC
D0 (LSB)
D1
VREF
SENSE
MODE
OTR
D11 (MSB)
D10
D9
D8
D
2
D
3
D
4
D
5
D
6
D
7
D
G
N
D
R
V
D
A
V
D
A
G
N
D
V
IN
–
V
IN
+
A
G
N
D
A
V
D
R
E
F
T
R
E
F
B
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
AD9237
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin Number
Mnemonic
Description
1
MODE2
SHA Gain Select and Power Scaling Control (see Table 8).
2
CLK
Clock Input Pin.
3
OE
Output Enable Pin (Active Low).
4
PDWN
Power-Down Function Selection (see Table 9).
5
GC
Gray Code Control (Active High).
6
DNC
Do Not Connect.
7 to 14, 17 to 20
D0 (LSB) to D11 (MSB)
Data Output Bits.
15
DGND
Digital Output Ground.
16
DRVDD
Digital Output Driver Supply. Must be decoupled to DGND with a minimum 0.1 μF capacitor.
Recommended decoupling is 0.1 μF in parallel with 10 μF.
21
OTR
Out-of-Range Indicator.
22
MODE
Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection (see Table 10).
23
SENSE
Reference Mode Selection (see Table 7).
24
VREF
Voltage Reference Input/Output (see Table 7).
25
REFB
Differential Reference (). Must be decoupled to REFT with a minimum 10 μF capacitor.
26
REFT
Differential Reference (+).
27, 32
AVDD
Analog Power Supply. Must be decoupled to AGND with a minimum 0.1 μF capacitor.
Recommended decoupling is 0.1 μF in parallel with 10 μF.
28, 31
AGND
Analog Ground.
29
VIN+
Analog Input Pin (+).
30
VIN
Analog Input Pin ().
EP
It is recommended that the exposed paddle be soldered to the ground plane. There is an
increased reliability of the solder joints and maximum thermal capability of the package is
achieved with exposed paddle soldered to the customer board.
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