AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; A" />
參數(shù)資料
型號： AD9238BSTZRL-65
廠商： Analog Devices Inc
文件頁數(shù)： 34/48頁
文件大小： 0K
描述： IC ADC 12BIT DUAL 65MSPS 64LQFP
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 12
采樣率（每秒）： 65M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 600mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個單端，單極；2 個差分，單極
AD9238
Rev. C | Page 4 of 48
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = 0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 1.
Test
AD9238BST/BCP-20
AD9238BST/BCP-40
AD9238BST/BCP-65
Parameter
Temp
Level
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
Full
VI
12
Bits
ACCURACY
No Missing Codes Guaranteed
Full
VI
12
Bits
Offset Error
Full
VI
±0.30
±1.2
±0.50
±1.1
±0.50
±1.1
% FSR
Gain Error1
Full
IV
±0.30
±2.2
±0.50
±2.4
±0.50
±2.5
% FSR
Differential Nonlinearity (DNL)2
V
±0.35
LSB
25°C
I
±0.35
±0.9
±0.35
±0.8
±0.35
±1.0
LSB
Integral Nonlinearity (INL)2
Full
V
±0.45
±0.60
±0.70
LSB
25°C
I
±0.40
±1.4
±0.50
±1.4
±0.55
±1.75
LSB
TEMPERATURE DRIFT
Offset Error
Full
V
±4
±6
μV/°C
Gain Error
Full
V
±12
ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Full
VI
±5
±35
±5
±35
±5
±35
mV
Load Regulation @ 1.0 mA
Full
V
0.8
mV
Output Voltage Error (0.5 V Mode)
Full
V
±2.5
mV
Load Regulation @ 0.5 mA
Full
V
0.1
mV
INPUT REFERRED NOISE
Input Span = 1 V
25°C
V
0.54
LSB rms
Input Span = 2.0 V
25°C
V
0.27
LSB rms
ANALOG INPUT
Input Span = 1.0 V
Full
IV
1
V p-p
Input Span = 2.0 V
Full
IV
2
V p-p
Input Capacitance3
Full
V
7
pF
REFERENCE INPUT RESISTANCE
Full
V
7
kΩ
POWER SUPPLIES
Supply Voltages
AVDD
Full
IV
2.7
3.0
3.6
2.7
3.0
3.6
2.7
3.0
3.6
V
DRVDD
Full
IV
2.25
3.0
3.6
2.25
3.0
3.6
2.25
3.0
3.6
V
Supply Current
Full
V
60
110
200
mA
Full
V
4
10
14
mA
PSRR
Full
V
±0.01
% FSR
POWER CONSUMPTION
DC Input4
Full
V
180
330
600
mW
Sine Wave Input2
Full
VI
190
212
360
397
640
698
mW
Standby Power5
Full
V
2.0
mW
MATCHING CHARACTERISTICS
Offset Error
25°C
V
±0.1
% FSR
Gain Error
25°C
V
±0.05
% FSR
1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
2 Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure
for the equivalent analog input structure.
4 Measured with dc input at maximum clock rate.
5 Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND).
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