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| 型號： | AD9239BCPZ-170 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT DUAL 170MSPS 72PIN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 170M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 1.22W |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 72-LFCSP |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 8 個(gè)單端，單極；4 個(gè)差分，單極 |
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Data Sheet
AD9239
Rev. C | Page 25 of 40
Table 10. Flexible Output Test Modes
Output Test Mode
Bit Sequence
Pattern Name
Digital Output Word 1
Digital Output Word 2
Subject to Data
Format Select
0000
Off (default)
N/A
Yes
0001
Midscale short
1000 0000 0000
Same
Yes
0010
+Full-scale short
1111 1111 1111
Same
Yes
0011
Full-scale short
0000 0000 0000
Same
Yes
0100
Checkerboard
1010 1010 1010
0101 0101 0101
No
0101
PN sequence long1
N/A
Yes
0110
PN sequence short1
N/A
Yes
0111
One-/zero-word toggle
1111 1111 1111
0000 0000 0000
No
1
All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver.
Register 14 allows the user to invert the digital outputs from
their nominal state. This is not to be confused with inverting
the serial stream to an LSB-first mode. In default mode, as
shown in Figure 2, the MSB is first in the data output serial
stream. However, this can be inverted so that the LSB is first in
the data output serial stream.
There are eight digital output test pattern options available that
can be initiated through the SPI. This feature is useful when
validating receiver capture and timing. Refer to Table 10 for the
output bit sequencing options available. Some test patterns have
two serial sequential words and can be alternated in various
ways, depending on the test pattern chosen. It should be noted
that some patterns do not adhere to the data format select
option. In addition, custom user-defined test patterns can be
assigned in the 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, and
0x20 register addresses.
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 29 1 or 511 bits. A description
of the PN sequence and how it is generated can be found in
Section 5.1 of the ITU-T 0.150 (05/96) standard. The only
difference is that the starting value must be a specific value
instead of all 1s (see Table 11 for the initial values).
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 223 1 or 8,388,607 bits. A
description of the PN sequence and how it is generated can be
found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The
only differences are that the starting value must be a specific
value instead of all 1s (see Table 11 for the initial values) and the
AD9239 inverts the bit stream with relation to the ITU standard.
Table 11. PN Sequence
Sequence
Initial
Value
First Three Output Samples
(MSB First)
PN Sequence Short
0x0df
0xdf9, 0x353, 0x301
PN Sequence Long
0x29b80a
0x591, 0xfd7, 0x0a3
Consult the Memory Map section for information on how to
change these additional digital output timing features through
the SPI.
Digital Output Scrambler and Error Code Correction
The data from the AD9239 is sent serially in packets of 64 bits.
These numbers are derived from the necessity to have the output
data streaming at 16× the encode clock. The data packets consist
of a header, data, and error correction code (that is, 8 Bits of
Header + 48 Bits of Data (4 Conv.) + 8 Bits of ECC = 64 Bits).
The 12-bit protocol is shown in Figure 2 and Table 5.
Error Correction Code
The error correction code (ECC) is a Hamming code due to the
ease of implementation. Seven bits are used for the ECC to
correct one error or detect one or two errors during transmission.
The MSB of the ECC is always 0 and is not used to detect an
error. The six LSBs of the ECC are the result of the XORs of the
given bits (see Figure 68 to Figure 75). These bits allow for a
parity check for any bit in the header and data field.
The seventh parity bit is applied to the entire packet after the
Hamming parity bits are calculated. This parity check allows
correction of an error in the data or in the ECC bits.
In the general implementation, the parity bits are located in the
power of 2 positions, but are pulled from these locations and
placed together at the end of the packet. Figure 68 to Figure 75
show which header and data bits are associated with the parity bits.
In the receiver, these parity checks are performed and the
receiver parity bits are calculated. The difference between the
received parity bits and the calculated parity bits indicate which
bit was in error.
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