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參數(shù)資料
| 型號： | AD9243ASZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT SGL 3MSPS 44MQFP |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 3M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 7 |
| 功率耗散（最大）： | 145mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；1 個(gè)差分，單極 |
AD9243
REV. A
–17–
The AD9243 contains an internal reference buffer, A2 (see
Figure 26), that simplifies the drive requirements of an external
reference. The external reference must be able to drive a
≈5 k
(
±20%) load. Note that the bandwidth of the reference buffer is
deliberately left small to minimize the reference noise contribu-
tion. As a result, it is not possible to change the reference volt-
age rapidly in this mode without the removal of the CAPT/
CAPB Decoupling Network, and driving these pins directly.
Variable Input Span with VCM = 2.5 V
Figure 39 shows an example of the AD9243 configured for an
input span of 2
× VREF centered at 2.5 V. An external 2.5 V
reference drives the VINB pin thus setting the common-mode
voltage at 2.5 V. The input span can be independently set by a
voltage divider consisting of R1 and R2 which generates the
VREF signal. A1 buffers this resistor network and drives VREF.
Choose this op amp based on accuracy requirements. It is
essential that a minimum of a 10
F capacitor in parallel with a
0.1
F low inductance ceramic capacitor decouple the reference
output to ground.
2.5V+VREF
2.5V–VREF
2.5V
+5V
0.1 F
22 F
VINA
VINB
VREF
SENSE
AD9243
+5V
R2
0.1 F
A1
R1
0.1 F
2.5V
REF
Figure 39. External Reference, VCM = 2.5 V (2.5 V on VINB,
Resistor Divider to Make VREF)
Single-Ended Input with 0 to 2
VREF Range
Figure 40 shows an example of an external reference driving
both VINB and VREF. In this case, both the common mode
voltage and input span are directly dependent on the value of
VREF. More specifically, the common-mode voltage is equal to
VREF while the input span is equal to 2
× VREF. Thus, the
valid input range extends from 0 to 2
× VREF. For example, if
the REF191, a 2.048 external reference was selected, the valid
input range extends from 0 V to 4.096 V. In this case, 1 LSB of
the AD9243 corresponds to 0.250 mV. It is essential that a
minimum of a 10
F capacitor in parallel with a 0.1 F low induc-
tance ceramic capacitor decouple the reference output to ground.
2xREF
0V
+5V
10 F
VINA
VINB
VREF
SENSE
AD9243
+5V
0.1 F
VREF
0.1 F
Figure 40. Input Range = 0 V to 2
× VREF
Low Cost/Power Reference
The external reference circuit shown in Figure 41 uses a low
cost 1.225 V external reference (e.g., AD580 or AD1580) along
with an op amp and transistor. The 2N2222 transistor acts in
conjunction with 1/2 of an OP282 to provide a very low imped-
ance drive for VINB. The selected op amp need not be a high
speed op amp and may be selected based on cost, power, and
accuracy.
3.75V
1.25V
+5V
10 F
VINA
VINB
VREF
SENSE
AD9243
+5V
0.1 F
316
1k
0.1 F
1/2
OP282
10 F
0.1 F
7.5k
AD1580
1k
820
+5V
2N2222
1.225V
Figure 41. External Reference Using the AD1580 and Low
Impedance Buffer
DIGITAL INPUTS AND OUTPUTS
Digital Outputs
The AD9243 output data is presented in positive true straight
binary for all input ranges. Table IV indicates the output data
formats for various input ranges regardless of the selected input
range. A twos complement output data format can be created by
inverting the MSB.
Table IV. Output Data Format
Input (V)
Condition (V)
Digital Output
OTR
VINA –VINB
< – VREF
00 0000 0000 0000 1
VINA –VINB
= – VREF
00 0000 0000 0000 0
VINA –VINB
= 0
10 0000 0000 0000 0
VINA –VINB
= + VREF – 1 LSB 11 1111 1111 1111 0
VINA –VINB
≥ + VREF
11 1111 1111 1111 1
111111 1111 1111
111111 1111 1110
OTR
–FS
+FS
–FS +1/2 LSB
+FS –1/2 LSB
–FS –1/2 LSB
+FS –1 1/2 LSB
000000 0000 0001
000000 0000 0000
1
0
1
OTR
DATA OUTPUTS
Figure 42. Output Data Format
Out Of Range (OTR)
An out-of-range condition exists when the analog input voltage
is beyond the input range of the converter. OTR is a digital
output that is updated along with the data output corresponding
to the particular sampled analog input voltage. Hence, OTR
has the same pipeline delay (latency) as the digital data. It is
LOW when the analog input voltage is within the analog input
range. It is HIGH when the analog input voltage exceeds the
input range as shown in Figure 42. OTR will remain HIGH
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