參數(shù)資料
型號(hào)： AD9248BCPZRL-65
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/48頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT DUAL 65MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 14
采樣率（每秒）： 65M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 600mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個(gè)單端，單極；2 個(gè)差分，單極
AD9248
Rev. B | Page 18 of 48
The minimum common-mode input level allows the AD9248 to
accommodate ground-referenced inputs. Although optimum
performance is achieved with a differential input, a single-ended
source may be driven into VIN+ or VIN. In this configuration,
one input accepts the signal, while the opposite input should be
set to midscale by connecting it to an appropriate reference. For
example, a 2 V p-p signal may be applied to VIN+, while a 1 V
reference is applied to VIN. The AD9248 then accepts an
input signal varying between 2 V and 0 V. In the single-ended
configuration, distortion performance may degrade significantly
as compared to the differential case. However, the effect is less
noticeable at lower input frequencies and in the lower speed grade
models (AD9248-40 and AD9248-20).
Differential Input Configurations
As previously detailed, optimum performance is achieved while
driving the AD9248 in a differential input configuration. For
baseband applications, the AD8138 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8138 is easily set to
AVDD/2, and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal.
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9248. This is especially true in IF
under-sampling applications where frequencies in the 70 MHz
to 200 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration, as shown in Figure 33.
AD9248
VINA
VINB
AVDD
AGND
2V p-p
50
Ω
50
Ω
10pF
49.9
Ω
1k
Ω
1k
Ω
0.1
μF
04446-032
Figure 33. Differential Transformer Coupling
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there is a
degradation in SFDR and distortion performance due to the
large input common-mode swing. However, if the source
impedances on each input are matched, there should be little
effect on SNR performance.
CLOCK INPUT AND CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive
to the clock duty cycle. Commonly, a 5% tolerance is required
on the clock duty cycle to maintain dynamic performance
characteristics.
The AD9248 provides separate clock inputs for each channel. The
optimum performance is achieved with the clocks operated at the
same frequency and phase. Clocking the channels asynchronously
may degrade performance significantly. In some applications, it
is desirable to skew the clock timing of adjacent channels. The
AD9248’s separate clock inputs allow for clock timing skew
(typically ±1 ns) between the channels without significant
performance degradation.
The AD9248-65 contains two clock duty cycle stabilizers, one
for each converter, that retime the nonsampling edge, providing
an internal clock with a nominal 50% duty cycle. When proper
track-and-hold times for the converter are required to maintain
high performance, maintaining a 50% duty cycle clock is
particularly important in high speed applications. It may be
difficult to maintain a tightly controlled duty cycle on the input
clock on the PCB (see Figure 24). DCS can be enabled by tying
the DCS pin high.
The duty cycle stabilizer uses a delay-locked loop to create the
nonsampling edge. As a result, any changes to the sampling
frequency require approximately 2 μs to 3 μs to allow the DLL
to acquire and settle to the new rate.
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (fINPUT) due only to aperture jitter (tJ) can be
calculated as
()
×
=
j
INPUT
t
f
π
SNR
2
1
log
20
In the equation, the rms aperture jitter, tJ , represents the root-
sum square of all jitter sources, which includes the clock input,
analog input signal, and ADC aperture jitter specification.
Under-sampling applications are particularly sensitive to jitter.
For optimal performance, especially in cases where aperture
jitter may affect the dynamic range of the AD9248, it is important
to minimize input clock jitter. The clock input circuitry should
use stable references; for example, use analog power and ground
planes to generate the valid high and low digital levels for the
AD9248 clock input. Power supplies for clock drivers should be
separated from the ADC output driver supplies to avoid modulating
the clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated from
another type of source (by gating, dividing, or other methods), it
should be retimed by the original clock at the last step.
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