AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; A
參數(shù)資料
型號: AD9248BCPZRL-65
廠商: Analog Devices Inc
文件頁數(shù): 46/48頁
文件大?。?/td> 0K
描述: IC ADC 14BIT DUAL 65MSPS 64LFCSP
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 14
采樣率(每秒): 65M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 600mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個單端,單極;2 個差分,單極
AD9248
Rev. B | Page 7 of 48
SWITCHING SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = 0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 4.
Test
AD9248BST/BCP-20
AD9248BST/BCP-40
AD9248BST/BCP-65
Parameter
Temp
Level
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
SWITCHING PERFORMANCE
Maximum Conversion Rate
Full
VI
20
40
65
MSPS
Minimum Conversion Rate
Full
V
1
MSPS
CLK Period
Full
V
50.0
25.0
15.4
ns
CLK Pulse-Width High1
Full
V
15.0
8.8
6.2
ns
CLK Pulse-Width Low1
Full
V
15.0
8.8
6.2
ns
DATA OUTPUT PARAMETER
Output Delay2 (tPD)
Full
VI
2
3.5
6
2
3.5
6
2
3.5
6
ns
Pipeline Delay (Latency)
Full
V
7
Cycles
Aperture Delay (tA)
Full
V
1.0
ns
Aperture Uncertainty (tJ)
Full
V
0.5
ps rms
Wake-Up Time3
Full
V
2.5
ms
OUT-OF-RANGE RECOVERY TIME
Full
V
2
Cycles
1 The AD9248-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 24).
2 Output delay is measured from clock 50% transition to data 50% transition, with a 5 pF load on each output.
3 Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
ANALOG
INPUT
CLOCK
DATA
OUT
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
MIN 2.0ns,
MAX 6.0ns
tPD =
04446-002
Figure 2. Timing Diagram
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