參數資料
型號: AD9252ABCPZRL7-50
廠商: Analog Devices Inc
文件頁數: 15/52頁
文件大?。?/td> 0K
描述: IC ADC 14BIT SRL 50MSPS 64LFCSP
標準包裝: 750
位數: 14
采樣率(每秒): 50M
數據接口: 串行,SPI?
轉換器數目: 8
功率耗散(最大): 773mW
電壓電源: 模擬和數字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應商設備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
輸入數目和類型: 16 個單端,單極;8 個差分,單極
AD9252
Data Sheet
Rev. E | Page 22 of 52
500
400
300
200
100
–500
–400
–300
–200
–100
0
–1.0ns
–1.5ns
–0.5ns
0ns
0.5ns
1.0ns
1.5ns
EYE
D
IA
G
R
A
M
VO
L
T
A
G
E
(m
V)
EYE: ALL BITS
ULS: 12071/12071
90
50
10
20
30
40
60
70
80
0
–150ps
–100ps
–50ps
0ps
50ps
100ps
150ps
TIE
J
ITTE
R
H
IS
TOGR
A
M
(
H
it
s
)
06296-
030
Figure 48. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Less Than 24 Inches on Standard FR-4
60
80
90
70
50
40
20
10
100
30
0
–200ps
–100ps
100ps
0ps
200ps
TIE
J
ITTE
R
H
IS
TOGR
A
M
(
H
it
s
)
500
400
300
200
100
–500
–400
–300
–200
–100
0
–1.0ns
–0.5ns
0ns
0.5ns
1.5ns
–1.5ns
1.0ns
EYE
D
IA
G
R
A
M
VO
L
T
A
G
E
(m
V)
EYE: ALL BITS
ULS: 12067/12067
06296-
028
Figure 49. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater Than 24 Inches on Standard FR-4
400
300
200
100
–400
–300
–200
–100
0
–0.5ns
0ns
0.5ns
EYE
D
IA
G
R
A
M
VO
L
T
A
G
E
(m
V)
EYE: ALL BITS
ULS: 12072/12072
80
50
10
20
30
40
60
70
0
–150ps
–100ps
–50ps
0ps
50ps
100ps
150ps
TIE
J
ITTE
R
H
IS
TOGR
A
M
(
H
it
s
)
–1.0ns
1.5ns
–1.5ns
1.0ns
06296-
029
Figure 50. Data Eye for LVDS Outputs in ANSI-644 Mode with 100
Termination On and Trace Lengths Greater Than 24 Inches on Standard FR-4
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 8.
To change the output data format to twos complement, see the
Memory Map section.
Table 8. Digital Output Coding
Code
(VIN + x) (VIN x),
Input Span = 2 V p-p (V)
Digital Output Offset Binary
(D13 ... D0)
16383
+1.00
11 1111 1111 1111
8192
0.00
10 0000 0000 0000
8191
0.000122
01 1111 1111 1111
0
1.00
00 0000 0000 0000
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 14 bits
times the sample clock rate, with a maximum of 700 Mbps
(14 bits × 50 MSPS = 700 Mbps). The lowest typical conversion
rate is 10 MSPS. However, if lower sample rates are required for
a specific application, the PLL can be set up via the SPI to allow
encode rates as low as 5 MSPS. See the Memory Map section for
information about enabling this feature.
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