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參數(shù)資料
| 型號： | AD9253TCPZ-125EP |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/40頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT SRL 125MSPS 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | LVDS，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 540mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個差分，雙極 |
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Data Sheet
AD9253
Rev. 0 | Page 35 of 40
ADDR
(Hex)
Parameter Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Comments
0x0B
Clock divide
(global)
Open
Clock divide ratio[2:0]
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
0x00
0x0C
Enhancement
control
Open
Chop
mode
0 = off
1 = on
Open
0x00
Enables/
disables chop
mode.
0x0D
Test mode (local
except for PN
sequence resets)
User input test mode
00 = single
01 = alternate
10 = single once
11 = alternate once
(affects user input test
mode only,
Bits[3:0] = 1000)
Reset
PN long
gen
Reset PN
short
gen
Output test mode[3:0] (local)
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = one/zero word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
0x00
When set, the
test data is
placed on the
output pins in
place of
normal data.
0x10
Offset adjust
(local)
8-bit device offset adjustment [7:0] (local)
Offset adjust in LSBs from +127 to 128 (twos complement format)
0x00
Device offset
trim.
0x14
Output mode
Open
LVDS-ANSI/
LVDS-IEEE
option
0 = LVDS-
ANSI
1 = LVDS-
IEEE
reduced
range link
(global)
see
Open
Output
invert
(local)
Open
Output
format
0 =
offset
binary
1 =
twos
comple-
ment
(global)
0x01
Configures
the outputs
and the
format of the
data.
0x15
Output adjust
Open
Output driver
termination[1:0]
00 = none
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω
Open
Output
drive
0 = 1×
drive
1 = 2×
drive
0x00
Determines
LVDS or other
output
properties.
0x16
Output phase
Open
Input clock phase adjust[6:4]
(value is number of input clock
cycles of phase delay)
see Table 19
Output clock phase adjust[3:0]
(0000 through 1011)
see Table 20
0x03
On devices
that use
global clock
divide,
determines
which phase
of the divider
output is used
to supply the
output clock.
Internal
latching is
unaffected.
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