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| 型號： | AD9279-65EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 27/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9279 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 8 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 串行 |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9279 |
| 已供物品： | 板 |
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AD9279
Rev. 0 | Page 33 of 44
The PN sequence long pattern produces a pseudo random bit
sequence that repeats itself every 223 1 bits, or 8,388,607 bits.
A description of the PN sequence long and how it is generated
can be found in Section 5.6 of the ITU-T O.150 (05/96) standard.
The only differences are that the starting value is a specific value
instead of all 1s and that the AD9279 inverts the bit stream with
relation to the ITU-T standard (see Table 14 for the initial
values).
Table 14. PN Sequence
Sequence
Initial
Value
First Three Output Samples
(MSB First)
PN Sequence Short
0x0DF
0xDF9, 0x353, 0x301
PN Sequence Long
0x29B80A
0x591, 0xFD7, 0x0A3
See the Memory Map section for information on how to change
these additional digital output timing features through the SPI.
SDIO Pin
This pin is required to operate the SPI. It has an internal 30 kΩ
pull-down resistor that pulls this pin low and is only 1.8 V
tolerant. If applications require that this pin be driven from a
3.3 V logic level, insert a 1 kΩ resistor in series with this pin to
limit the current.
SCLK Pin
This pin is required to operate the SPI port interface. It has an
internal 30 kΩ pull-down resistor that pulls this pin low and is
both 1.8 V and 3.3 V tolerant.
CSB Pin
This pin is required to operate the SPI port interface. It has an
internal 70 kΩ pull-up resistor that pulls this pin high and is
both 1.8 V and 3.3 V tolerant.
RBIAS Pin
To set the internal core bias current of the ADC, place a resistor
nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using a
resistor other than the recommended 10.0 kΩ resistor for RBIAS
degrades the performance of the device. Therefore, it is imperative
that at least a 1% tolerance on this resistor be used to achieve
consistent performance.
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the
AD9279. This is gained up internally by a factor of 2, setting
VREF to 1.0 V, which results in a full-scale differential input span
of 2.0 V p-p for the ADC. VREF is set internally by default, but
the VREF pin can be driven externally with a 1.0 V reference to
achieve more accuracy. However, the AD9279 does not support
ADC full-scale ranges below 2.0 V p-p.
When applying the decoupling capacitors to the VREF pin,
use ceramic, low ESR capacitors. These capacitors should be
close to the reference pin and on the same layer of the PCB as
the AD9279. The VREF pin should have both a 0.1 μF capacitor
and a 1 μF capacitor connected in parallel to the analog ground.
These capacitor values are recommended for the ADC to
properly settle and acquire the next valid sample.
The reference settings can be selected using the SPI. The settings
allow two options: using the internal reference or using an
external reference. The internal reference option is the default
setting and has a resulting differential span of 2 V p-p.
Table 15. SPI-Selectable Reference Settings
SPI-Selected Mode
Resulting
VREF (V)
Resulting Differential
Span (V p-p)
External Reference
N/A
2 × external reference
Internal Reference (Default)
1.0
2.0
CW DOPPLER OPERATION
Each channel of the AD9279 includes a I/Q demodulator. Each
demodulator has an individual programmable phase shifter. The
I/Q demodulator is ideal for phased array beamforming applica-
tions in medical ultrasound. Each channel can be programmed
for 16 delay states/360° (or 22.5°/step), selectable via the SPI port.
The part has a RESET input used to synchronize the LO dividers of
each channel. If multiple AD9279s are used, a common RESET
across the array ensures a synchronized phase for all channels.
Internal to the AD9279, the individual Channel I and Channel Q
outputs are current summed. If multiple AD9279s are used, the
I and Q outputs from each AD9279 can be current summed and
converted to a voltage using an external transimpedance amplifier.
Quadrature Generation
The internal 0° and 90° LO phases are digitally generated by
a divide-by-4 logic circuit. The divider is dc-coupled and
inherently broadband; the maximum LO frequency is limited
only by its switching speed. The duty cycle of the quadrature LO
signals is intrinsically 50% and is unaffected by the asymmetry
of the externally connected 4LO input. Furthermore, the divider
is implemented such that the 4LO signal reclocks the final flip-
flops that generate the internal LO signals and, thereby,
minimizes noise introduced by the divide circuitry.
For optimum performance, the 4LO input is driven differen-
tially, as on the AD9279 evaluation board (see the Ordering
Guide). The common-mode voltage on each pin is approx-
imately 1.2 V with the nominal 3 V supply. It is important to
ensure that the LO source have very low phase noise (jitter), a
fast slew rate, and an adequate input level to obtain optimum
performance of the CW signal chain.
Beamforming applications require a precise channel-to-channel
phase relationship for coherence among multiple channels. A
RESET pin is provided to synchronize the LO divider circuits
in different AD9279s when they are used in arrays. The RESET
pin resets the dividers to a known state after power is applied to
multiple AD9279s. Accurate channel-to-channel phase matching
can only be achieved via a common pulse on the RESET pin when
using more than one AD9279.
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