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參數(shù)資料
| 型號(hào)： | AD9284BCPZRL7-250 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT 250MSPS 1.8V 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 250M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 330mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)差分，雙極 |
| 配用： | AD9284-250EBZ-ND - BOARD EVAL FOR AD9284 |
AD9284
Data Sheet
Rev. A | Page 14 of 24
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9284 sample clock inputs,
CLK+ and CLK with a differential signal. The signal is typically
ac-coupled into the CLK+ and CLK pins via a transformer or
capacitors.
Clock Input Options
The AD9284 has a very flexible clock input structure. The clock
input can be an LVDS, LVPECL, or sine wave signal. Each configu-
ration that is described in this section applies to CLK+ and CLK.
Figure 21 and Figure 22 show the two preferred methods for
clocking the AD9284. A low jitter clock source is converted
from a single-ended signal to a differential signal using either
an RF transformer or an RF balun. The back-to-back Schottky
diodes across the transformer/balun secondary limit clock
excursions into the AD9284 to approximately 0.8 V p-p
differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9284, while
preserving the fast rise and fall times of the signal that are
critical to low jitter performance.
0.1F
SCHOTTKY
DIODES:
HSM2822
50 100
CLK–
CLK+
ADC
Mini-Circuits
ADT1-1WT, 1:1 Z
XFMR
CLOCK
INPUT
09085-
027
Figure 21. Transformer-Coupled Differential Clock
0.1F
SCHOTTKY
DIODES:
HSM2822
1nF
50
CLK–
CLK+
ADC
CLOCK
INPUT
09085-
028
Figure 22. Balun-Coupled Differential Clock
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
excellent jitter performance.
10
0
0.1F
240
50k
CLK–
CLK+
ADC
AD951x
PECL DRIVER
CLOCK
INPUT
CLOCK
INPUT
09085-
029
Figure 23. Differential PECL Sample Clock
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 24. The AD9510/
clock drivers offer excellent jitter performance.
10
0
0.1F
50k
CLK–
CLK+
ADC
AD951x
LVDS DRIVER
CLOCK
INPUT
CLOCK
INPUT
09085-
030
Figure 24. Differential LVDS Sample Clock
DIGITAL OUTPUTS
Digital Output Enable Function (OE)
The AD9284 has a flexible three-state ability for the digital output
pins. The three-state mode is enabled using the OE pin. When
OE is set to logic level high, the output drivers for both data buses
are placed into a high impedance state.
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