參數(shù)資料
型號(hào): AD9286BCPZ-500
廠商: Analog Devices Inc
文件頁數(shù): 25/28頁
文件大小: 0K
描述: IC ADC 8BIT SPI/SRL 500M 48LFSCP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 8
采樣率(每秒): 500M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 330mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 托盤
輸入數(shù)目和類型: 2 個(gè)差分,雙極
AD9286
Data Sheet
Rev. B | Page 6 of 28
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted.
Table 4.
Parameter
Temperature
Min
Typ
Max
Unit
CLOCK INPUT PARAMETERS
Input Clock Rate
Full
60
500
MHz
CLK Period (tCLK)
Full
2
ns
CLK Pulse Width High (tCH)
Full
1
ns
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)
3.7
ns
DCO Propagation Delay (tDCO)
Full
3.7
ns
DCO to Data Skew (tSKEW)
Full
280
60
100
ps
Pipeline Delay (Latency)
Full
11
Cycles
Aperture Delay (tA)
Full
1.0
ns
Aperture Uncertainty (Jitter, tJ)
Full
0.1
ps rms
Wake-Up Time1
Full
500
μs
OUT-OF-RANGE RECOVERY TIME
Full
4
Cycles
1 Wake-up time is dependent on the value of the decoupling capacitors.
SPI TIMING SPECIFICATIONS
Table 5.
Parameter
Description
Min
Typ
Max
Unit
SPI TIMING REQUIREMENTS
tDS
Setup time between the data and the rising edge of SCLK
2
ns
tDH
Hold time between the data and the rising edge of SCLK
2
ns
tCLK
Period of the SCLK
40
ns
tS
Setup time between CSB and SCLK
2
ns
tH
Hold time between CSB and SCLK
2
ns
tHIGH
SCLK pulse width high
10
ns
tLOW
SCLK pulse width low
10
ns
tEN_SDIO
Time required for the SDIO pin to switch from an input
to an output relative to the SCLK falling edge
10
ns
tDIS_SDIO
Time required for the SDIO pin to switch from an output
to an input relative to the SCLK rising edge
10
ns
Timing Diagrams
09
338-
002
N – 1
N – 2
N + 1
M – 11 N – 11 M – 10 N – 10 M – 9
N – 9
M – 8
M – 7
N – 8
N + 2
N + 4
N + 3
N
tCH
tCLK
M + 5
M + 4
M + 3
M + 1
M + 2
tA
M
M – 1
VIN1+, VIN1–
VIN2+, VIN2–
CLK+
CLK–
DCO+, DCO–
DATA
tA
tDCO
tSKEW
tPD
Figure 2. Output Timing Diagram, Sample Mode = Interleaved (Default)
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