參數(shù)資料
型號(hào)： AD9289BBC
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/32頁(yè)
文件大小： 0K
描述： IC ADC 8BIT QUAD 65MSPS 64CSPBGA
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 8
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 625mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 64-CSPBGA（8x8）
包裝： 托盤(pán)
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)差分，單極
AD9289
Rev. 0 | Page 17 of 32
Table 9. Data Format Configuration
DFS Mode
Data Format
AVDD
Twos complement
AGND
Offset binary
Timing
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to eight
bits times the sample clock rate, with a maximum of 520 MHz
(8 bits x 65 MSPS = 520 MHz). The lowest typical conversion
rate is 12 MSPS.
Two output clocks are provided to assist in capturing data from
the AD9289. The DCO is used to clock the output data and is
equal to four times the sampling clock (CLK) rate. Data is
clocked out of the AD9289 and can be captured on the rising
and falling edges of the DCO that supports double-data rate
operation (DDR). The frame clock out (FCO) signals the start
of a new output byte and is equal to the sampling clock rate. See
the timing diagram shown in Figure 2 for more information.
LOCK Pin
The AD9289 contains an internal PLL that is used to generate
the DCO. When the PLL is locked, the LOCK signal will be low,
indicating valid data on the outputs.
If for any reason the PLL loses lock, the LOCK signal goes high
as soon as the lock circuitry detects an unlocked condition.
While the PLL is unlocked, the data outputs and DCO remains
in the last known state. If the LOCK signal goes high in the
middle of a byte, no data or DCO signals will be available for
the rest of the byte. It takes at least 1.8 s at 65 MSPS to regain
lock once it is lost. Note that regaining lock is sample rate-
dependent and takes at least 100 input periods after the PLL
acquires the input clock.
Once the PLL regains lock the DCO starts. The first valid data
byte is indicated by the FCO signal. The FCO rising edge occurs
0.5 to <1.5 input clock periods after LOCK goes low.
CML Pin
A common-mode level output is available at Pin F3. This output
self biases to AVDD/2. This is a relatively high impedance
output (2.5k nominal), which may need to be considered when
used as a reference.
DTP Pin
When the digital test pattern (DTP) pin is enabled (pulled to
AVDD), all of the ADC channel outputs shift out the following
pattern: 11000000. The FCO and DCO outputs still work as
usual while all channels shift out the test pattern. This pattern
allows the user to perform timing alignment adjustments
between the DCO and the output data.
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the
AD9289. The input range can be adjusted by varying the refer-
ence voltage applied to the AD9289, using either the internal
reference or an externally applied reference voltage. The input
span of the ADC tracks reference voltage changes linearly.
The shared reference mode (see Figure 32) allows the user to
externally connect the reference buffers from the quad ADC for
better gain and offset matching performance. If the ADCs are to
function independently, the reference decoupling can be treated
independently and can provide better isolation between the four
channels. To enable shared reference mode, the SHARED_REF
pin must be tied high and external reference buffer decoupling
pins must be externally shorted. (REFT_A must be externally
shorted to REFT_B and REFB_A must be shorted to REFB_B.)
Note that Channels A and B are referenced to REFT_A and
REFB_A and Channels C and D are referenced to REFT_B
and REFB_B.
Table 10. Reference Settings
Selected Mode
SENSE
Voltage
Resulting
VREF (V)
Resulting
Differential Span
(V p-p)
External
Reference
AVDD
N/A
2 × External
Reference
Internal,
1 V p-p FSR
VREF
0.5
1.0
Programmable
0.2 V to
VREF
0.5 ×
(1 + R2/R1)
2 × VREF
Internal,
2 V p-p FSR
AGND to
0.2 V
1.0
2.0
Internal Reference Connection
A comparator within the AD9289 detects the potential at the
SENSE pin and configures the reference into four possible
states, which are summarized in Table 10. If SENSE is grounded,
the reference amplifier switch is connected to the internal resis-
tor divider (see Figure 33), setting VREF to 1 V. Connecting the
SENSE pin to the VREF pin switches the amplifier output to the
SENSE pin, configuring the internal op amp circuit as a voltage
follower and providing a 0.5 V reference output. If an external
resistor divider is connected as shown in Figure 34 the switch is
again set to the SENSE pin. This puts the reference amplifier in
a noninverting mode with the VREF output defined as
+
×
=
R1
R2
VREF
1
5
.
0
In all reference configurations, REFT_A and REFT_B and
REFB_A and REFB_B establish their input span of the ADC
core. The input range of the ADC always equals twice the
voltage at the reference pin for either an internal or an external
reference.
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