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| 型號： | AD9393BBCZ-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 27/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE 80MHZ HDMI 76CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 視頻 |
| 接口： | HDMI |
| 電源電壓： | 3.15 V ~ 3.47 V |
| 封裝/外殼： | 76-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 76-CSPBGA（6x6） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 775 (CN2011-ZH PDF) |
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AD9393
Rev. 0 | Page 33 of 40
PCB LAYOUT RECOMMENDATIONS
The AD9393 is a high precision, high speed digital device. To
achieve the maximum performance from the part, it is impor-
tant to have a well laid-out board. The following sections are a
guide for designing a board using the AD9393.
POWER SUPPLY BYPASSING
It is recommended to bypass each power supply ball with a
0.1 μF capacitor. The exception is in the case where two or
more supply pins are adjacent to each other. For these groupings
of powers/grounds, it is only necessary to have one bypass
capacitor. The fundamental idea is to have a bypass capacitor
within about 0.5 cm of each power ball. Also, avoid placing
the capacitor on the opposite side of the PC board from the
AD9393, because that interposes resistive vias in the path.
The bypass capacitors should be physically located between the
power plane and the power ball. Current should flow from the
power plane to the capacitor to the power ball. Do not make the
power connection between the capacitor and the power ball.
Placing a via underneath the capacitor pads down to the power
plane is generally the best approach.
It is particularly important to maintain low noise and good
stability of PVDD (the clock generator supply). Abrupt changes
in PVDD can result in similarly abrupt changes in sampling
clock phase and frequency. This can be avoided by paying
careful attention to regulation, filtering, and bypassing. It is
highly desirable to provide separate regulated supplies for
each of the circuitry groups (VD and PVDD).
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during HSYNC and VSYNC periods). This can result in a
measurable change in the voltage supplied to the regulator,
which can in turn produce changes in the regulated supply
voltage. This can be mitigated by regulating the PVDD from a
different, cleaner power source (for example, from a 12 V supply).
It is recommended to use a single ground plane for the entire
board. Experience has shown repeatedly that the noise perfor-
mance is the same or better with a single ground plane. Using
multiple ground planes can be detrimental because each separate
ground plane is smaller and long ground loops can result.
In some cases, using separate ground planes is unavoidable, so
it is recommended to place a single ground plane under the
AD9393. The location of the split should be at the receiver of
the digital outputs. In this case, it is even more important to
place components wisely because the current loops are much
longer (current takes the path of least resistance).
OUTPUTS (BOTH DATA AND CLOCKS)
Try to minimize the trace length that the digital outputs have
to drive. Longer traces have higher capacitance, which require
more current that causes more internal digital noise.
Shorter traces reduce the possibility of reflections.
Adding a series resistor of value 50 Ω to 200 Ω can suppress
reflections, reduce EMI, and reduce the current spikes inside
the AD9393. If series resistors are used, place them as close as
possible to the AD9393 pins (although try not to add vias or
extra length to the output trace to move the resistors closer).
If possible, limit the capacitance that each of the digital outputs
drives to less than 10 pF. This can be accomplished easily by
keeping traces short and by connecting the outputs to only one
device. Loading the outputs with excessive capacitance increases
the current transients inside of the AD9393 and creates more
digital noise on its power supplies.
DIGITAL INPUTS
The digital inputs on the AD9393 are designed to work with
3.3 V signals, but are tolerant of 5.0 V signals. Therefore, no
extra components need to be added if using 5.0 V logic.
Any noise that enters the HSYNC input trace can add jitter to
the system. Therefore, minimize the trace length and do not run
any digital or other high frequency traces near it.
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| AD9393BBCZRL-80 | 功能描述:IC INTERFACE 80MHZ HDMI 76CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9394BCBZ-R7 | 功能描述:IC INTERFACE HDMI 12WLCSP RoHS:是 類別:集成電路 (IC) >> PMIC - 電源管理 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:手持/移動設(shè)備 電流 - 電源:- 電源電壓:3 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:14-LLP-EP（4x4） 包裝:Digi-Reel® 配用:LP3905SD-30EV-ND - BOARD EVALUATION LP3905SD-30 其它名稱:LP3905SD-30DKR |
| AD9396 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Analog/DVI Dual-Display Interface |
| AD9396/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Analog/DVI Dual-Display Interface |
| AD9396KSTZ-100 | 制造商:Analog Devices 功能描述:Analog/DVI Dual Display Interface 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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