參數(shù)資料
型號: AD9393BBCZ-80
廠商: Analog Devices Inc
文件頁數(shù): 3/40頁
文件大?。?/td> 0K
描述: IC INTERFACE 80MHZ HDMI 76CSPBGA
標(biāo)準(zhǔn)包裝: 1
應(yīng)用: 視頻
接口: HDMI
電源電壓: 3.15 V ~ 3.47 V
封裝/外殼: 76-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 76-CSPBGA(6x6)
包裝: 托盤
安裝類型: 表面貼裝
產(chǎn)品目錄頁面: 775 (CN2011-ZH PDF)
AD9393
Rev. 0 | Page 11 of 40
AUDIO BOARD LEVEL MUTING
The audio can be muted through the infoframes or locally
via the serial bus registers. This can be controlled with
Register 0x57, Bits[7:6].
AVI Infoframes
The HDMI TMDS transmission contains infoframes with
specific information for the monitor such as:
Audio information
Two channels to eight channels of audio identified
Audio coding
Audio sampling frequency
Speaker placement
N and CTS values (for reconstruction of the audio)
Muting
Source information
CD
SACD
DVD
Video information
Video ID code (per CEA861B)
Color space
Aspect ratio
Horizontal and vertical bar information
MPEG frame information (I, B, or P frame)
Vendor (transmitter source) name and product model
This information is the fundamental difference between DVI
and HDMI transmissions and is located in the read-only registers
Register 0x5A to Register 0xEE. In addition to this information,
registers are provided to indicate that new information has been
received. Registers with addresses ending in 7 or F beginning
with Register 0x87 contain the new data flags (NDF)
information. All of these registers contain the same information
and all are reset when any of them are read. Although there is
no external interrupt signal, it is very easy for the user to read
any of the NDF registers to see if there is new information to be
processed.
OUTPUT DATA FORMATS
The AD9393 supports 4:4:4, 4:2:2, double data-rate (DDR), and
BT656 output formats. Register 0x25[3:0] controls the output
mode. These modes and the pin mapping are illustrated in
Table 8. Output Formats1
Port
Bits D[23:0]
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
4:4:4
Red/Cr [7:0]
Green/Y [7:0]
Blue/Cb [7:0]
4:2:2
CbCr [7:0]
Y [7:0]
DDR 4:2:2 CbCr Y, Y
4:4:4 DDR
DDR G [3:0]
DDR B [7:4]
DDR B [3:0]
DDR 4:2:2 CbCr [11:0]
DDR R [7:0]
DDR G [7:4]
DDR 4:2:2 Y, Y [11:0]
4:2:2 to 12-bit
CbCr [11:0]
Y [11:0]
1 Arrows indicate clock edge. The rising edge of clock =
↑, the falling edge = ↓.
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