參數(shù)資料
型號(hào)： AD9444BSVZ-80
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/40頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT 80MSPS 100TQFP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 80M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1.4W
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
輸入數(shù)目和類型： 1 個(gè)差分，單極
AD9444
Rev. 0 | Page 13 of 40
Table 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS Mode
Pin No.
Mnemonic
Description
1, 8 to 9, 16 to 18,
24 to 27, 34 to 35,
38, 41 to 42, 87,
89 to 95, 98
AVDD1
3.3 V (±5%) Analog Supply.
2 to 4, 7,
43 to 46, 49 to 52,
55 to 60, 65
DNC
Do Not Connect. These
pins should float.
5
OUTPUT
MODE
CMOS Compatible Output
Logic Mode Control Pin.
OUTPUT MODE = 0 for CMOS
mode, and OUTPUT MODE =
1 (AVDD1) for LVDS outputs.
6
DFS
Data Format Select Pin.
CMOS control pin that de-
termines the format of the
output data. DFS = high
(AVDD1) for twos comple-
ment, DFS = low (ground) for
offset binary format.
10
SENSE
Reference Mode Selection.
Connect to AGND for internal
1 V reference, and connect to
AVDD2 for external reference.
11
VREF
1.0 V Reference I/O—
Function Dependent on
SENSE. Decouple to ground
with 0.1 F and 10 F
capacitors.
12, 15, 20, 23,
32, 86, 88, 96 to
97, 99, Exposed
Heat Sink
AGND
Analog Ground. The exposed
heat sink on the bottom of
the package must be
connected to AGND.
13
REFT
Differential Reference Out-
put. Decoupled to ground
with 0.1 F capacitor and to
REFB (Pin 14) with 0.1 F and
10 F capacitors.
14
REFB
Differential Reference Out-
put. Decoupled to ground
with a 0.1 F capacitor and to
REFT (Pin 13) with 0.1 F and
10 F capacitors.
19, 28 to 31,
39 to 40
AVDD2
5.0 V Analog Supply (±5%).
21
VIN+
Analog Input—True.
22
VIN
Analog Input—Complement.
Pin No.
Mnemonic
Description
33
C1
Internal Bypass Node.
Connect a 0.1 F capacitor
from this pin to AGND.
36
CLK+
Clock Input—True.
37
CLK
Clock Input—Complement.
47, 54, 62,
75, 83
DRVDD
3.3 V Digital Output
Supply (2.5V to 3.6 V).
48, 53, 61,
67, 74, 82
DRGND
Digital Ground.
63
DCO
Data Clock Output—
Complement (CMOS Levels).
64
DCO+
Data Clock Output—
True.
66
D0 (LSB)
D0 Output Bit (LSB)
(CMOS Levels).
68
D1
D1 Output Bit.
69
D2
D2 Output Bit.
70
D3
D3 Output Bit.
71
D4
D4 Output Bit.
72
D5
D5 Output Bit.
73
D6
D6 Output Bit.
76
D7
D7 Output Bit.
77
D8
D8 Output Bit.
78
D9
D9 Output Bit.
79
D10
D10 Output Bit.
80
D11
D11 Output Bit.
81
D12
D12 Output Bit.
84
D13 (MSB)
D13 Output Bit.
85
OR
Out-of-Range Output.
100
DCS MODE
Clock Duty Cycle Stabilizer
(DCS) Control Pin, CMOS-
Compatible. DCS = low
(AGND) to enable DCS
(recommended). DCS =
high (AVDD1) to disable DCS.
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