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| 型號： | AD9445BSVZ-125 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/40頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 125MSPS 100-TQFP |
| 設(shè)計(jì)資源： | Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002) Using AD8352 as an Ultralow Distortion Differential RF/IF Front End for High Speed ADCs (CN0046) Using ADL5562 Differential Amplifier to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0110) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.6W |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極 |
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14-Bit, 105/125 MSPS, IF Sampling ADC
AD9445
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2005 Analog Devices, Inc. All rights reserved.
FEATURES
125 MSPS guaranteed sampling rate (AD9445BSV-125)
78.3 dBFS SNR/92 dBFS SFDR with 30 MHz input (3.2 V p-p)
74.8 dBFS SNR/95 dBFS SFDR with 30 MHz input (2.0 V p-p)
77.0 dBFS SNR/87 dBFS SFDR with 170 MHz input (3.2 V p-p)
74.6 dBFS SNR/95 dBFS SFDR with 170 MHz input (2.0 V p-p)
73.0 dBFS SNR/88 dBFS SFDR with 300 MHz input (2.0 V p-p)
102 dBFS 2-tone SFDR with 30 MHz and 31 MHz
92 dBFS 2-tone SFDR with 170 MHz and 171 MHz
60 fsec rms jitter
Excellent linearity
DNL = ±0.25 LSB typical
INL = ±0.8 LSB typical
2.0 V p-p to 4.0 V p-p differential full-scale input
Buffered analog inputs
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos complement)
Output clock available
3.3 V and 5 V supply operation
APPLICATIONS
Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar
Infrared imaging
Medical imaging
Communications instrumentation
GENERAL DESCRIPTION
The AD9445 is a 14-bit, monolithic, sampling analog-to-digital
converter (ADC) with an on-chip IF sampling track-and-hold
circuit. It is optimized for performance, small size, and ease of
use. The product operates at up to a 125 MSPS conversion rate
and is designed for multicarrier, multimode receivers, such as
those found in cellular infrastructure equipment.
The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are CMOS or LVDS
compatible (ANSI-644 compatible) and include the means to
reduce the overall current needed for short trace distances.
FUNCTIONAL BLOCK DIAGRAM
CMOS
OR
LVDS
OUTPUT
STAGING
CLOCK
AND TIMING
MANAGEMENT
AGND
DRGND DRVDD
VREF
CLK+
VIN+
AD9445
VIN–
CLK–
DCO
05489-001
AVDD1 AVDD2
DCS MODE
DFS
RF ENABLE
OUTPUT MODE
T/H
BUFFER
14
PIPELINE
ADC
2
28
2
OR
D13 TO D0
REF
REFB
SENSE REFT
Figure 1.
Optional features allow users to implement various selectable
operating conditions, including input range, data format select,
high IF sampling mode, and output data mode.
The AD9445 is available in a Pb-free, 100-lead, surface-mount,
plastic package (100-lead TQFP/EP) specified over the
industrial temperature range 40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
High performance: outstanding SFDR performance for IF
sampling applications such as multicarrier, multimode 3G,
and 4G cellular base station receivers.
2.
Ease of use: on-chip reference and high input impedance
track-and-hold with adjustable analog input range and an
output clock simplifies data capture.
3.
Packaged in a Pb-free, 100-lead TQFP/EP package.
4.
Clock duty cycle stabilizer (DCS) maintains overall ADC
performance over a wide range of clock pulse widths.
5.
OR (out-of-range) outputs indicate when the signal is
beyond the selected input range.
6.
RF enable pin allows users to configure the device for
optimum SFDR when sampling frequencies above 210 MHz
(AD9445-125) or 240 MHz (AD9445-105).
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9445-IF-LVDS | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 105/125 MSPS, IF Sampling ADC |
| AD9445-IF-LVDS/PCB | 制造商:Analog Devices 功能描述:Evaluation Kit For 14-Bit, 105/125 MAPA, IF Sampling ADC 制造商:Analog Devices 功能描述:EVAL KIT FOR 14BIT, 105/125 MSPS, IF SAMPLING ADC - Bulk |
| AD9445IF-LVDS/PCBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD9445IF 制造商:Analog Devices 功能描述:14-BIT 125 MSPS ADC IF EVAL BD - Bulk |
| AD9445-IF-LVDSPCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Speed ADC USB FIFO Evaluation Kit |
| AD9445-IF-PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 105/125 MSPS, IF Sampling ADC |
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