參數(shù)資料
型號(hào)： AD9446-100LVDS
廠商： Analog Devices, Inc.
英文描述： 16-Bit, 80/100 MSPS ADC
中文描述： 16位，80/100 MSPS的模數(shù)轉(zhuǎn)換器
文件頁數(shù)： 26/36頁
文件大?。?/td> 952K
代理商： AD9446-100LVDS
AD9446
Rev. 0 | Page 26 of 36
0
0.1
μ
F
R
T
AD9446
VIN+
VIN–
R
S
R
S
ADT1–1WT
ANALOG
INPUT
SIGNAL
Figure 58. Transformer-Coupled Analog Input Circuit
CLOCK INPUT CONSIDERATIONS
Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer, and any noise, distortion, or timing jitter on
the clock is combined with the desired signal at the analog-to-
digital output. For that reason, considerable care was taken in
the design of the clock inputs of the AD9446, and the user is
advised to give careful thought to the clock source.
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive
to the clock duty cycle. Commonly a 5% tolerance is required on
the clock duty cycle to maintain dynamic performance charac-
teristics. The AD9446 contains a clock duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal ~50% duty cycle. Noise and distortion per-
formance are nearly flat for a 30% to 70% duty cycle with the DCS
enabled. The DCS circuit locks to the rising edge of CLK+ and
optimizes timing internally. This allows for a wide range of input
duty cycles at the input without degrading performance. Jitter in
the rising edge of the input is still of paramount concern and is
not reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates of less than 30 MHz
nominally. The loop is associated with a time constant that
should be considered in applications where the clock rate can
change dynamically, requiring a wait time of 1.5 μs to 5 μs after a
dynamic clock frequency increase or decrease before the DCS
loop is relocked to the input signal. During the time that the
loop is not locked, the DCS loop is bypassed, and the internal
device timing is dependent on the duty cycle of the input clock
signal. In such an application, it may be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the duty cycle stabilizer,
and logic high (AVDD1 = 3.3 V) disables the controller.
The AD9446 input sample clock signal must be a high quality,
extremely low phase noise source to prevent degradation of per-
formance. Maintaining 16-bit accuracy places a premium on the
encode clock phase noise. SNR performance can easily degrade
high jitter clock source. (See the
AN-501 Application Note
,
optimum performance, the AD9446 must be clocked differentially.
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