參數(shù)資料
型號(hào): AD9446-100LVDS
廠商: Analog Devices, Inc.
英文描述: 16-Bit, 80/100 MSPS ADC
中文描述: 16位,80/100 MSPS的模數(shù)轉(zhuǎn)換器
文件頁(yè)數(shù): 3/36頁(yè)
文件大小: 952K
代理商: AD9446-100LVDS
AD9446
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 3.2 V p-p differential input, internal
trimmed reference (1.6 V mode), A
IN
= 1.0 dBFS, DCS on, unless otherwise noted.
Table 1.
Parameter
Temp
RESOLUTION
Full
ACCURACY
No Missing Codes
Full
Offset Error
Full
Gain Error
Full
25°C
Differential Nonlinearity (DNL)
1
Full
Integral Nonlinearity (INL)
1
25°C
VOLTAGE REFERENCE
Output Voltage
1
VREF = 1.6 V (3.2 V p-p Analog Input Range)
Full
Load Regulation @ 1.0 mA
Full
Reference Input Current (External 1.6 V Reference)
Full
INPUT REFERRED NOISE
25°C
ANALOG INPUT
Input Span
VREF = 1.6 V
Full
VREF = 1.0 V (External)
Full
Internal Input Common-Mode Voltage
Full
External Input Common-Mode Voltage
Full
Input Resistance
2
Full
Input Capacitance
2
Full
POWER SUPPLIES
Supply Voltage
AVDD1
Full
AVDD2
Full
DRVDD—LVDS Outputs
Full
DRVDD—CMOS Outputs
Full
Supply Current
I
AVDD1
Full
I
AVDD21
Full
I
DRVDD1
—LVDS Outputs
Full
I
DRVDD1
—CMOS Outputs
Full
PSRR
Offset
Full
Gain
Full
POWER CONSUMPTION
LVDS Outputs
Full
CMOS Outputs (DC Input)
Full
1
Measured at the maximum clock rate, f
= 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and
approximately 5 pF loading on each output bit for CMOS output mode.
2
Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.
Rev. 0 | Page 3 of 36
AD9446BSVZ-80
Min
Typ
16
Guaranteed
5
±0.1
3
±0.6
2
±0.3
0.75
±0.4
5
±3.0
1.6
±2
1.5
3.2
2.0
3.5
3.2
1
6
3.14
3.3
4.75
5.0
3.0
3.3
3.0
3.3
335
204
68
14
1
0.2
2.4
2.2
AD9446BSVZ-100
Min
Typ
16
Guaranteed
5
±0.1
3
±0.5
2
±0.3
0.85
±0.4
6
±3.0
1.6
±2
1.9
3.2
2.0
3.5
3.2
1
6
3.14
3.3
4.75
5.0
3.0
3.3
3.0
3.3
368
223
69
14
1
0.2
2.6
2.3
Unit
Bits
mV
% FSR
% FSR
LSB
LSB
V
mV
μA
LSB rms
V p-p
V p-p
V
V
pF
V
V
V
V
mA
mA
mA
mA
mV/V
%/V
W
W
Max
Max
+5
+3
+2
+0.75
+5
3.8
3.46
5.25
3.6
3.6
365
234
75
2.6
+5
+3
+2
+0.85
+6
3.8
3.46
5.25
3.6
3.6
401
255
75
2.8
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