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參數(shù)資料
型號(hào)： AD9481-PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/28頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL 8BIT 250MSPS 44-TQFP
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 8
采樣率（每秒）： 250M
數(shù)據(jù)接口： 并聯(lián)
輸入范圍： 1 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 439mW @ 250MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9481
已供物品： 板
相關(guān)產(chǎn)品： AD9481BSUZ-250-ND - IC ADC 8BIT 250MSPS 3.3V 44-TQFP
AD9481
Rev. 0 | Page 20 of 28
Table 9. S1 Voltage Levels
S1 Voltage
Data Format
Duty Cycle
Stabilizer
(0.9 × AVDD)
→ AVDD
Offset binary
Disabled
(2/3 × AVDD) ± (0.1 × AVDD)
Offset binary
Enabled
(1/3 × AVDD) ± (0.1 × AVDD)
Twos complement
Enabled
AGND
→ (0.1 × AVDD)
Twos complement
Disabled
DIGITAL OUTPUTS
The CMOS digital outputs are TTL-/CMOS-compatible for
lower power consumption. The outputs are biased from a
separate supply (DRVDD), allowing easy interface to external
logic. The outputs are CMOS devices that swing from ground to
DRVDD (with no dc load). It is recommended to minimize the
capacitive load the ADC drives by keeping the output traces
short (< 2 inch, for a total CLOAD < 5 pF). When operating in
CMOS mode, it is also recommended to place low value series
damping resistors on the data lines close to the ADC to reduce
switching transient effects on performance.
Table 10. Output Coding (FS = 1 V)
Code
(VIN+) (VIN)
Offset Binary
Twos Complement
255
> +0.512 V
1111 1111
0111 1111
255
+0.512 V
1111 1111
0111 1111
254
+0.508 V
1111 1110
0111 1110
129
+0.004 V
1000 0001
0000 0001
128
+0.0 V
1000 0000
0000 0000
127
0.004 V
0111 1111
1111 1111
2
0.504 V
0000 0010
1000 0010
1
0.508 V
0000 0001
1000 0001
0
0.512 V
0000 0000
1000 0000
0
< 0.512 V
0000 0000
1000 0000
INTERLEAVING TWO AD9481s
Instrumentation applications may prefer to interleave (or ping-
pong) two AD9481s to achieve twice the sample rate, or
500 MSPS. In these applications, it is important to match the
gain and offset of the two ADCs. Varying the reference voltage
allows the gain of the ADCs to be adjusted; external dc offset
compensation can be used to reduce offset mismatch between
two ADCs. The sampling phase offset between the two ADCs
is extremely important as well and requires very low skew
between clock signals driving the ADCs (< 2 ps clock skew
for a 100 MHz analog input frequency).
DATA CLOCK OUT
A data clock is available at DCO+ and DCO. These clocks can
facilitate latching off-chip, providing a low skew clocking
solution. The on-chip delay of the DCO clocks tracks with the
on-chip delay of the data bits, (under similar loading) such that
the variation between tPD and tCPD is minimized. It is
recommended to keep the trace lengths on the data and DCO
pins matched and 2 inches maximum. A series damping resistor
at the clock outputs is also recommended. The DCO outputs
can be disabled and placed in a high impedance state by tying
S3 to ground (tie to AVDD for DCO active). Switching both
into and out of high impedance is accomplished in 4 ns from S3
switching.
POWER-DOWN INPUT
The ADC can be placed into a low power state by setting the
PDWN pin to AVDD. Time to go into (or come out of) power
down equals 30 ns typically from PDWN switching.
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