- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373963 > AD9483 (Analog Devices, Inc.) Triple 8-Bit, 140 MSPS A/D Converter PDF資料下載
參數(shù)資料
| 型號： | AD9483 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Triple 8-Bit, 140 MSPS A/D Converter |
| 中文描述： | 三8位，140 MSPS的A / D轉換 |
| 文件頁數(shù)： | 14/26頁 |
| 文件大小： | 319K |
| 代理商： | AD9483 |
AD9483
–14–
REV. A
ADC Gain Control
Each of the three ADC channels has independent limited gain
control. The full-scale signal amplitude for a given ADC is set by
the dc voltage on its VREF In pin. The equation relating the full
scale amplitude to VREF In is as follows: FS = (0.4)
×
(VREF
IN). The three ADCs are optimized for a full-scale signal ampli-
tude of 1 V, but will accommodate up to
±
10% variation.
ADC Offset Control
The offset for each of the three ADCs can be independently
controlled. For a single-ended analog input where the analog
input is connected to a reference, offset can be adjusted simply
by adjusting the dc voltage of the reference. For differential
analog inputs, the user must provide the offset in their signal.
Offset can be adjusted up or down as far as the common-mode
input range will allow.
Power Dissipation
Power dissipation for the AD9483 has two components, V
CC
and V
DD
. Power dissipation from V
CC
is relatively constant for a
given supply voltage, whereas power dissipation from V
DD
can
vary greatly. V
CC
supplies power to the analog circuity. V
DD
supplies power to the digital outputs and can be approximated
by the following equation:
P
(
V
DD
) = 1/2
C
×
V
2
×
F
×
N
C
= Output Load Capacitance
V
= V
DD
Supply Voltage
F
= Encode Frequency
N
= Number of Outputs Switching
Nominally, C = 10 pF, V = 3.3 V, F = 140 MSPS, and N = 26.
N comes from the 24 output bits plus two clock outputs, P(V
DD
) =
197 mW.
Power-Down
The power-down function allows users to reduce power dissipa-
tion when output data is not required. A TTL/CMOS HIGH
signal on pin 76, (PD), shuts down most of the chip and brings
the total power dissipation to less than 100 mW. The internal
bandgap voltage reference remains active during power-down
mode to minimize reactivation time. If the power-down function
is not desired, the PD pin should be tied to ground or held to a
TTL/CMOS LOW level.
Bandgap Voltage Reference
The AD9483 internal reference, VREF OUT (Pin 97), provides
a simple, cost effective reference for many applications. It exhib-
its reasonable accuracy and excellent stability over power supply
and temperature variations. The reference output can be used to
set the three ADCs’ gain and offset. The reference is capable of
providing up to 1 mA of additional current beyond the require-
ments of the AD9483.
As the ADC gain and offset are set by the reference inputs,
some applications may require a reference with greater accuracy
or temperature performance. In these cases, an external refer-
ence may be connected directly to the VREF IN pins. VREF
OUT, if unused, should be left floating. Note, each of the three
VREF IN pins will require up to 1 mA of current.
Modes of Operation
The AD9483 has three modes of operation, Single Channel
output mode, and a Dual Channel output mode with two pos-
sible data formats, interleaved or parallel. Two pins control which
mode of operation the chip is in, Pin 74 Output Mode Select
(OMS) and Pin 75 Interleaved/Parallel Select (I/P). Table II
shows the configuration required for each mode.
Table II. Output Mode Selection
MODE
OMS
I/P
Dual Channel—Parallel
Dual Channel—Interleaved
Single Channel
LOW
LOW
HIGH
LOW
HIGH
DON’T CARE
Demuxed Output Mode
In demuxed mode, (Pin 74 OMS = LOW), the ADC output
data are alternated between the two output ports (Port A and
Port B). This limits the data output rate to 1/2 the rate of
ENCODE, and facilitates conversion rates up to 140 MSPS.
Demuxed output mode is recommended for guaranteed opera-
tion above 100 MSPS, but may be enabled at any specified
conversion rate.
Two data formats are possible in Dual Channel output mode,
parallel data out and interleaved data out. Pin 75 I/P should be
LOW for parallel format and HIGH for interleaved format.
Figures 1 and 2 show the timing requirements for each format.
Note that the Data Sync input, (DS), is required in Dual Chan-
nel output mode for both formats. The section on Data Sync
describes the requirements of the Data Sync input.
As shown in Figures 1 and 2, when using the interleaved data
format, a sample is taken on an ENCODE rising edge N. The
resulting data is produced on an output port following the fifth
rising edge of ENCODE after the sample was taken, (five pipe-
line delays). The following sample, (N+1), will be produced on
the opposite port, also five pipeline delays after it was taken.
The state of CLKOUT when the sample was taken will deter-
mine out of which port the data will come. If CLKOUT was
LOW, the data will come out Port A. If CLKOUT was HIGH,
the data will come out Port B.
In order to achieve parallel data format on the two output data
ports, the data is internally aligned. This is accomplished by
adding an extra pipeline delay to just the A Data Port. Thus,
data coming out Port A will have six pipeline delays and data
coming out Port B will have five pipeline delays. As with the
interleaved format, the state of Data Sync when a sample is
taken will determine out of which port the data will come. If
CLKOUT was LOW, the data will come out Port A. If CLK-
OUT was HIGH, the data will come out Port B.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9500 | Digitally Programmable Delay Generator |
| AD9500BP | Digitally Programmable Delay Generator |
| AD9500BQ | Digitally Programmable Delay Generator |
| AD9500TE | Digitally Programmable Delay Generator |
| AD9500TQ | Digitally Programmable Delay Generator |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9483/PCB | 制造商:Analog Devices 功能描述: |
| AD9483KS-100 | 制造商:Analog Devices 功能描述:ADC Triple Flash 100Msps 8-bit Parallel 100-Pin MQFP 制造商:Analog Devices 功能描述:ADC TRIPLE FLASH 100MSPS 8BIT PARALLEL 100MQFP - Trays |
| AD9483KS-140 | 制造商:Analog Devices 功能描述:Triple ADC Flash 140Msps 8-bit Parallel 100-Pin MQFP 制造商:Analog Devices 功能描述:ADC TRIPLE FLASH 140MSPS 8BIT PARALLEL 100MQFP - Trays |
| AD9484 | 制造商:AD 制造商全稱:Analog Devices 功能描述:8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter Excellent linearity |
| AD9484-500EBZ | 功能描述:BOARD EVAL W/AD9484BCPZ-500 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉換器 (ADC) 系列:- 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
發(fā)布緊急采購，3分鐘左右您將得到回復。