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參數(shù)資料
| 型號： | AD9483KS-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Triple 8-Bit, 140 MSPS A/D Converter |
| 中文描述： | 3-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP100 |
| 封裝： | HEAT SINK, PLASTIC, MQFP-100 |
| 文件頁數(shù)： | 13/26頁 |
| 文件大?。?/td> | 319K |
| 代理商： | AD9483KS-100 |
AD9483
–13–
REV. A
APPLICATION NOTES
Theory of Operation
The AD9483 combines Analog Devices’ patented MagAmp bit-
per-stage architecture with flash converter technology to create a
high performance, low power ADC. For ease of use the part
includes an on board reference and input logic that accepts
TTL, CMOS or PECL levels.
Each of the three analog input signals is buffered by a high speed
differential amplifier and applied to a track-and-hold (T/H)
circuit. This T/H captures the value of the input at the sampling
instant and maintains it for the duration of the conversion. The
sampling and conversion process is initiated by a rising edge on
the ENCODE input. Once the signal is captured by the T/H,
the four Most Significant Bits (MSBs) are sequentially encoded
by the MagAmp string. The residue signal is then encoded by a
flash comparator string to generate the four Least Significant
Bits (LSBs). The comparator outputs are decoded and com-
bined into the 8-bit result.
If the user has selected Single Channel mode (OMS = HIGH)
the 8-bit data word is directed to an A output bank. Data are
strobed to the output on the rising edge of the ENCODE input
with four pipeline delays. If the user has selected Dual Channel
mode (OMS = LOW) the data are alternately directed between
the A and B output banks and the data has five pipeline delays.
At power-up, the N sample data can appear at either the A or B
Port. To align the data in a known state, the user must strobe
DATA SYNC (DS,
DS
) per the conditions described in the
Timing section.
Graphics Applications
The high bandwidth and low power of the AD9483 makes it
very attractive for applications that require the digitization of
presampled waveforms, wherein the input signal rapidly slews
from one level to another, then is relatively stable for a period of
time. Examples of these include digitizing the output of com-
puter graphic display systems, and very high speed solid state
imagers.
These applications require the converter to process inputs with
frequency components well in excess of the sampling rate (often
with subnanosecond rise times), after which the A/D must settle
and sample the input in well under one pixel time. The architec-
ture of the AD9483 is vastly superior to older flash architec-
tures, which not only exhibit excessive input capacitance (which
is very hard to drive), but can make major errors when fed a
very rapidly slewing signal. The AD9483’s extremely wide
bandwidth Track/Hold circuit processes these signals without
difficulty.
Using the AD9483
Good high speed design practices must be followed when using
the AD9483. Decoupling capacitors should be physically as
close as possible to the chip to obtain maximum benefit. We
recommend placing a 0.1
μ
F capacitor at each power ground
pin pair (14 total) for high frequency decoupling and including
one 10
μ
F capacitor for local low frequency decoupling. Each of
the three VREF IN pins should also be decoupled by a 0.1
μ
F
capacitor.
The part should be located on a solid ground plane and output
trace lengths should be short (<1 inch) to minimize transmis-
sion line effects. This will avoid the need for termination resis-
tors on the output bus and reduces the load capacitance that
needs to be driven, which in turn minimizes on-chip noise due
to heavy current flow in the outputs. We have obtained opti-
mum performance on our evaluation board by tying all V
CC
pins
to a quiet analog power supply system and tying all GND pins
to a quiet analog system ground.
Minimum Encode Rate
The minimum sampling rate for the AD9483 is 10 MHz for the
140 MSPS and 100 MSPS versions. To achieve this sampling
rate, the Track/Hold circuit employs a very small hold capacitor.
When operated below the minimum guaranteed sampling rate,
the T/H droop becomes excessive. This is first observed as an
increase in offset voltage, followed by degraded linearity at even
lower frequencies.
Lower effective sampling rates may be easily supported by oper-
ating the converter in Dual Port output mode and using only
one output channel. A majority of the power dissipated by the
AD9483 is static (not related to conversion rate), so the penalty
for clocking at twice the desired rate is not high.
Digital Inputs
SNR performance is directly related to the sampling clock sta-
bility in A/D converters, particularly for high input frequencies
and wide bandwidths.
ENCODE and Data Select (DS) can be driven differentially or
single-ended. For single-ended operation, the complement
inputs (
ENCODE
,
DS
) are internally biased to V
DD
/3 (~1.5 V)
by a high impedance on-chip resistor divider (Figure 5), but
they may be externally driven to establish an alternate threshold
if desired. A 0.1
μ
F decoupling capacitor to ground is sufficient
to maintain a threshold appropriate for TTL or CMOS logic.
When driven differentially, ENCODE and DS will accommo-
date differential signals centered between 1.5 V and 4.5 V with a
total differential swing
≥
800 mV (V
ID
≥
400 mV).
Note the 6-diode clock input protection circuitry in Figure 5.
This limits the differential input voltage to
±
2.1 V. When the
diodes turn on, current is limited by the 300
series resistor.
Exceeding 2.1 V across the differential inputs will have no im-
pact on the performance of the converter, but be aware of the
clock signal distortion that may be produced by the nonlinear
impedance at the converter.
V
ID
V
ID
V
IH D
V
IC M
V
IL D
V
IN D
V
IC M
V
IL D
ENC
ENC
CLOCK
CLOCK
ENC
ENC
CLOCK
0.1
m
F
DRIVING DIFFERENTIAL INPUTS DIFFERENTIALLY
DRIVING DIFFERENTIAL INPUTS SINGLE-ENDEDLY
Figure 34. Input Signal Level Definitions
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