參數(shù)資料
型號(hào)： AD9484-500EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/24頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL W/AD9484BCPZ-500
設(shè)計(jì)資源： AD9434 Eval Brd Schematic
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 8
采樣率（每秒）： 500M
數(shù)據(jù)接口： 串行，SPI?
輸入范圍： 1.5 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 670mW @ 500MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9484
已供物品： 板
AD9484
Rev. A | Page 17 of 24
differential output traces be kept close together and at equal
lengths.
An example of the LVDS output using the ANSI standard (default)
data eye and a time interval error (TIE) jitter histogram with
trace lengths less than 24 inches on regular FR-4 material is
shown in Figure 36. Figure 37 shows an example of when the
trace lengths exceed 24 inches on regular FR-4 material. Notice
that the TIE jitter histogram reflects the decrease of the data eye
opening as the edge deviates from the ideal position. It is up to
the user to determine if the waveforms meet the timing budget
of the design when the trace lengths exceed 24 inches.
500
–500
–400
–300
–200
–100
0
100
200
300
400
–3
–2
–1
0
1
2
3
TIME (ns)
14
12
10
8
6
4
2
0
–40
–20
0
20
40
T
IE
JI
T
E
R
HI
S
T
O
G
RAM
(
H
it
s)
TIME (ps)
E
Y
E
DI
AG
RAM
:
V
O
LT
AG
E
(
m
V
)
09
61
5-
02
0
Figure 36. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less
Than 24 Inches on Standard FR-4
E
Y
E
DI
AG
RA
M
:V
O
LT
AG
E
(
m
V
)
600
–600
–400
–200
0
200
400
–3
–2
–1
0123
TIME (ns)
12
10
8
6
4
2
0
–100
0
100
TI
E
JITT
E
R
H
IS
TO
G
R
A
M
(H
it
s)
TIME (ps)
09
61
5-
0
21
Figure 37. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths
Greater Than 24 Inches on Standard FR-4
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 11.
If it is desired to change the output data format to twos comple-
An output clock signal is provided to assist in capturing data
from the AD9484. The DCO is used to clock the output data
and is equal to the sampling clock (CLK) rate. In single data
rate mode (SDR), data is clocked out of the AD9484 and must
be captured on the rising edge of the DCO. See the timing
diagram shown in Figure 2 for more information.
Output Data Rate and Pinout Configuration
The output data of the AD9484 can be configured to drive
12 pairs of LVDS outputs at the same rate as the input clock
signal (SDR mode).
Out-of-Range (OR)
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OR+ and OR (OR±)
are digital outputs that are updated along with the data output
corresponding to the particular sampled input voltage. Thus,
OR± has the same pipeline latency as the digital data. OR± is
low when the analog input voltage is within the analog input
range and high when the analog input voltage exceeds the input
range, as shown in Figure 38. OR± remains high until the analog
input returns to within the input range and another conversion
is completed. By logically AND’ing OR± with the MSB and its
complement, overrange high or underrange low conditions can
be detected.
1
0
1
OR± DATA OUTPUTS
OR±
+FS – 1 LSB
+FS – 1/2 LSB
+FS
–FS
–FS + 1/2 LSB
–FS – 1/2 LSB
1111
0000
1111
1110
0001
0000
0
961
5-
022
Figure 38. OR± Relation to Input Voltage and Output Data
TIMING
The AD9484 provides latched data outputs with a pipeline delay
of 15 clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD9484. These transi-
ents can degrade the dynamic performance of the converter.
The AD9484 also provides a data clock output (DCO) intended
for capturing the data in an external register. The data outputs
are valid on the rising edge of DCO.
The lowest conversion rate of the AD9484 is 50 MSPS. At clock
rates below 1 MSPS, the AD9484 assumes the standby mode.
VREF
The AD9484 VREF pin (Pin 31) allows the user to monitor the
on-board voltage reference, or provide an external reference
(requires configuration through the SPI). The three optional
settings are internal VREF (pin is connected to 20 kΩ to ground),
export VREF, and import VREF. Do not attach a bypass capacitor
to this pin. VREF is internally compensated and additional
loading may impact performance.
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