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參數(shù)資料
| 型號(hào)： | AD9484BCPZRL7-500 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 13/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT 500MSPS 56LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 500M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 720mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類(lèi)型： | 1 個(gè)差分，雙極 |
AD9484
Rev. A | Page 20 of 24
MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map table (see Table 12) has eight
address locations. The memory map is roughly divided into
three sections: chip configuration register map (Address 0x00 to
Address 0x02), transfer register map (Address 0xFF), and ADC
functions register map (Address 0x08 to Address 0x2A).
The Addr. (Hex) column of the memory map indicates the register
address in hexadecimal, and the Default Value (Hex) column
shows the default hexadecimal value that is already written into
the register. The Bit 7 (MSB) column is the start of the default
hexadecimal value given. For example, Hexadecimal Address
0x2A, OVR_CONFIG, has a hexadecimal default value of 0x01.
This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0,
Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. The
default value enables the OR± output. Overwriting this default so
that Bit 0 = 0 disables the OR± output. For more information on
this and other functions, consult the AN-877 Application Note,
Interfacing to High-Speed ADCs via SPI user manual at
RESERVED LOCATIONS
Undefined memory locations should not be written to other
than with the default values suggested in this data sheet. Addresses
that have values marked as 0 should be considered reserved and
have a 0 written into their registers during power-up.
DEFAULT VALUES
Coming out of reset, critical registers are preloaded with default
values. These values are indicated in Table 12. Other registers
do not have default values and retain the previous value when
exiting reset.
LOGIC LEVELS
An explanation of various registers follows: “Bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
Table 12. Memory Map Register
Addr.
(Hex)
Register Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default Notes/
Comments
Chip Configuration Registers
00
CHIP_PORT_CONFIG
0
LSB
first
Soft
reset
1
Soft
reset
LSB
first
0
0x18
The nibbles
should be
mirrored by the
user so that LSB
or MSB first
mode registers
correctly,
regardless of
shift mode.
01
CHIP_ID
8-bit chip ID, Bits[7:0] = 0x6C
Read
only
Default is a
unique chip ID,
different for
each device.
This is a read-
only register.
02
CHIP_GRADE
0
Speed grade:
00 = 500 MSPS
Read
only
Child ID used to
differentiate
graded devices.
Transfer Register
FF
DEVICE_UPDATE
0
SW
transfer
0x00
Synchronously
transfers data
from the master
shift register to
the slave.
ADC Functions Registers
08
Modes
0
PDWN:
0 = full
(default)
1 =
standby
0
Internal power-down mode:
000 = normal (power-up,
default)
001 = full power-down
010 = standby
011 = normal (power-up)
Note that external PDWN pin
overrides this setting
0x00
Determines
various generic
modes of chip
operation.
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