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參數(shù)資料
| 型號： | AD9484BCPZRL7-500 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 8BIT 500MSPS 56LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 500M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 720mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
AD9484
Rev. A | Page 15 of 24
AD9484
AD8352
0
R
0
CD
RD
RG
0.1F
VIN+
VIN– CML
C
0.1F
16
1
2
3
4
5
11
R
0.1F
10
8, 13
14
VCC
200
ANALOG INPUT
09
615
-015
Figure 30. Differential Input Configuration Using the AD8352
100
0.1F
240
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
501
CLK
150 RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADC
AD9484
PECL DRIVER
CLOCK
INPUT
CLOCK
INPUT
0
9615
-017
Figure 31. Differential PECL Sample Clock
100
0.1F
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
501
CLK
150 RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADC
AD9484
LVDS DRIVER
CLOCK
INPUT
CLOCK
INPUT
0
9615
-018
Figure 32. Differential LVDS Sample Clock
CLOCK INPUT CONSIDERATIONS
For optimum performance, drive the AD9484 sample clock
inputs (CLK+ and CLK) with a differential signal. This signal
is typically ac-coupled into the CLK+ and CLK pins via a
transformer or capacitors. These pins are biased at ~0.9 V
internally and require no additional bias. If the clock signal is
dc-coupled, then the common-mode voltage should remain
within a range of 0.9 V.
Figure 33 shows one preferred method for clocking the AD9484.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9484 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9484 and preserves the fast
rise and fall times of the signal, which are critical to low jitter
performance.
0.1F
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
AD9484
MINI-CIRCUITS
ADT1–1WT, 1:1Z
XFMR
SCHOTTKY
DIODES:
HSM2812
09
61
5-
0
16
Figure 33. Transformer-Coupled Differential Clock
If a low jitter clock is available, another option is to ac couple a
differential PECL signal to the sample clock input pins, as
performance.
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate,
and bypass the CLK pin to ground with a 0.1 μF capacitor in
parallel with a 39 kΩ resistor (see Figure 34).
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