- 您現(xiàn)在的位置：買賣IC網 > PDF目錄9158 > AD9517-1ABCPZ (Analog Devices Inc)IC CLOCK GEN 2.5GHZ VCO 48LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9517-1ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 37/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 2.5GHZ VCO 48LFCSP |
| 標準包裝： | 1 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:12 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.65GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LFCSP |
| 供應商設備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當前第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
AD9517-1
Data Sheet
Rev. E | Page 42 of 80
To connect the LVPECL outputs directly to the internal VCO or
CLK, the VCO divider must be selected as the source to the
distribution section, even if no channel uses it.
Either the internal VCO or the CLK can be selected as the
source for the direct-to-output routing.
Table 31. Settings for Routing VCO Divider Input Directly
to LVPECL Outputs
Register Setting
Selection
0x1E1[1:0] = 00b
CLK is the source; VCO divider selected
0x1E1[1:0] = 10b
VCO is the source; VCO divider selected
0x192[1] = 1b
Direct to OUT0 and OUT1 outputs
0x198[1] = 1b
Direct to OUT2 and OUT3 outputs
Clock Frequency Division
The total frequency division is a combination of the VCO
divider (when used) and the channel divider. When the VCO
divider is used, the total division from the VCO or CLK to the
output is the product of the VCO divider (2, 3, 4, 5, and 6) and
the division of the channel divider. Table 32 and Table 33
indicate how the frequency division for a channel is set. For the
LVPECL outputs, there is only one divider per channel. For the
LVDS/ CMOS outputs, there are two dividers (X.1, X.2)
cascaded per channel.
Table 32. Frequency Division for Divider 0 and Divider 1
CLK
or VCO
Selected
VCO
Divider
Channel
Divider
Direct to
Output
Frequency
Division
CLK/VCO
2 to 6
1 (bypassed)
Yes
1
CLK/VCO
2 to 6
1 (bypassed)
No
(2 to 6) × (1)
CLK/VCO
2 to 6
2 to 32
No
(2 to 6) ×
(2 to 32)
CLK
Not used
1 (bypassed)
No
1
CLK
Not used
2 to 32
No
2 to 32
Table 33. Frequency Division for Divider 2 and Divider 3
CLK
or VCO
Selected
VCO
Divider
Channel Divider
Frequency
Division
X.1
X.2
CLK/VCO
2 to 6
1
(bypassed)
1
(bypassed)
(2 to 6) ×
(1) × (1)
CLK/VCO
2 to 6
2 to 32
1
(bypassed)
(2 to 6) ×
(2 to 32) × (1)
CLK/VCO
2 to 6
2 to 32
(2 to 6) ×
(2 to 32) ×
(2to 32)
CLK
Not used
1
CLK
Not used
2 to 32
1
(2 to 32) × (1)
CLK
Not used
2 to 32
2 to 32 ×
(2 to 32)
The channel dividers feeding the LVPECL output drivers
contain one 2-to-32 frequency divider. This divider provides for
division by 2 to 32. Division by 1 is accomplished by bypassing
the divider. The dividers also provide for a programmable duty
cycle, with optional duty-cycle correction when the divide ratio
is odd. A phase offset or delay in increments of the input clock
cycle is selectable. The channel dividers operate with a signal at
their inputs up to 1600 MHz. The features and settings of the
dividers are selected by programming the appropriate setup
and control registers (see Table 52 through Table 62).
VCO Divider
The VCO divider provides frequency division between the
internal VCO or the external CLK input and the clock
distribution channel dividers. The VCO divider can be set
to divide by 2, 3, 4, 5, or 6 (see Table 60, Register 0x1E0[2:0]).
Channel Dividers—LVPECL Outputs
Each pair of LVPECL outputs is driven by a channel divider.
There are two channel dividers (0, 1) driving four LVPECL
outputs (OUT0 to OUT3). Table 34 gives the register locations
used for setting the division and other functions of these
dividers. The division is set by the values of M and N. The
divider can be bypassed (equivalent to divide-by-1, divider circuit
is powered down) by setting the bypass bit. The duty-cycle
correction can be enabled or disabled according to the setting of
the DCCOFF bits.
Divider
Low Cycles
M
High Cycles
N
Bypass
DCCOFF
0
0x190[7:4]
0x190[3:0]
0x191[7]
0x192[0]
1
0x196[7:4]
0x196[3:0]
0x197[7]
0x198[0]
1
Note that the value stored in the register = # of cycles minus 1.
Channel Frequency Division (0, 1)
For each channel (where the channel number is x: 0, 1), the
frequency division, DX, is set by the values of M and N
(four bits each, representing Decimal 0 to Decimal 15), where
Number of Low Cycles = M + 1
Number of High Cycles = N + 1
The cycles are cycles of the clock signal currently routed to the
input of the channel dividers (VCO divider out or CLK).
When a divider is bypassed, DX = 1.
Otherwise, DX = (N + 1) + (M + 1) = N + M + 2. This allows
each channel divider to divide by any integer from 2 to 32.
相關PDF資料 |
PDF描述 |
|---|---|
| V110A48H300BL2 | CONVERTER MOD DC/DC 48V 300W |
| AD9511BCPZ | IC CLOCK DIST 5OUT PLL 48LFCSP |
| V110A48H300BL | CONVERTER MOD DC/DC 48V 300W |
| VI-B60-MV | CONVERTER MOD DC/DC 5V 150W |
| AD9518-2ABCPZ | IC CLOCK GEN 6CH 2.2GHZ 48LFCSP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9517-1ABCPZ-RL7 | 功能描述:IC CLOCK GEN 2.5GHZ VCO 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9517-1BCPZ | 制造商:Analog Devices 功能描述:Clock Generator 48-Pin LFCSP EP Tray 制造商:Analog Devices 功能描述:CLOCK GEN 12-OUTPUT VCO LFCSP-48 |
| AD9517-1BCPZ-REEL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9517-1BCPZ-REEL7 | 制造商:Analog Devices 功能描述: |
| AD9517-2A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9517-2A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
發(fā)布緊急采購，3分鐘左右您將得到回復。