參數(shù)資料
型號(hào)： AD9517-1ABCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/80頁(yè)
文件大小： 0K
描述： IC CLOCK GEN 2.5GHZ VCO 48LFCSP
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 時(shí)鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:12
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.65GHz
除法器/乘法器： 是/無(wú)
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LFCSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 托盤(pán)
Data Sheet
AD9517-1
Rev. E | Page 15 of 80
POWER DISSIPATION
Table 17.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER DISSIPATION, CHIP
Power-On Default
1.0
1.2
W
No clock; no programming; default register values;
does not include power dissipated in external resistors
Full Operation; CMOS Outputs at 206 MHz
1.4
2.0
W
PLL on; internal VCO = 2476 MHz; VCO divider = 2;
all channel dividers on; six LVPECL outputs at 619 MHz;
eight CMOS outputs (10 pF load) at 206 MHz; all fine
delay on, maximum current; does not include power
dissipated in external resistors
Full Operation; LVDS Outputs at 206 MHz
1.4
2.1
W
PLL on; internal VCO = 2476 MHz, VCO divider = 2;
all channel dividers on; six LVPECL outputs t 619 MHz;
four LVDS outputs at 206 MHz; all fine delay on, maximum
current; does not include power dissipated in external resistors
PD Power-Down
75
185
mW
PD pin pulled low; does not include power dissipated
in terminations
PD Power-Down, Maximum Sleep
31
mW
PD pin pulled low; PLL power-down, Register 0x010[1:0] = 01b;
SYNC power-down, Register 0x230[2] = 1b; REF for
distribution power-down, Register 0x230[1] = 1b
VCP Supply
4
4.8
mW
PLL operating; typical closed-loop configuration
POWER DELTAS, INDIVIDUAL FUNCTIONS
Power delta when a function is enabled/disabled
VCO Divider
30
mW
VCO divider bypassed
REFIN (Differential)
20
mW
All references off to differential reference enabled
REF1, REF2 (Single-Ended)
4
mW
All references off to REF1 or REF2 enabled; differential
reference not enabled
VCO
70
mW
CLK input selected to VCO selected
PLL
75
mW
PLL off to PLL on, normal operation; no reference enabled
Channel Divider
30
mW
Divider bypassed to divide-by-2 to divide-by-32
LVPECL Channel (Divider Plus Output Driver)
160
mW
No LVPECL output on to one LVPECL output on, independent
of frequency
LVPECL Driver
90
mW
Second LVPECL output turned on, same channel
LVDS Channel (Divider Plus Output Driver)
120
mW
No LVDS output on to one LVDS output on; see Figure 8 for
dependence on output frequency
LVDS Driver
50
mW
Second LVDS output turned on, same channel
CMOS Channel (Divider Plus Output Driver)
100
mW
Static; no CMOS output on to one CMOS output on; see
Figure 9 for variation over output frequency
CMOS Driver (Second in Pair)
0
mW
Static; second CMOS output, same pair, turned on
CMOS Driver (First in Second Pair)
30
mW
Static; first output, second pair, turned on
Fine Delay Block
50
mW
Delay block off to delay block enabled; maximum current setting
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9517-1ABCPZ-RL7 功能描述:IC CLOCK GEN 2.5GHZ VCO 48LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類(lèi)型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
AD9517-1BCPZ 制造商:Analog Devices 功能描述:Clock Generator 48-Pin LFCSP EP Tray 制造商:Analog Devices 功能描述:CLOCK GEN 12-OUTPUT VCO LFCSP-48
AD9517-1BCPZ-REEL 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD9517-1BCPZ-REEL7 制造商:Analog Devices 功能描述:
AD9517-2A/PCBZ 功能描述:BOARD EVALUATION FOR AD9517-2A RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱(chēng):82EBV2081
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