參數(shù)資料
型號： AD9517-2ABCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 4/80頁
文件大?。?/td> 0K
描述： IC CLOCK GEN 2.2GHZ VCO 48LFCSP
標準包裝： 1
類型： 時鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:12
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.33GHz
除法器/乘法器： 是/無
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應商設備封裝： 48-LFCSP-VQ（7x7）
包裝： 托盤
AD9517-2
Data Sheet
Rev. E | Page 12 of 80
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include
PLL and VCO; uses rising edge of clock signal
CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1
40
fs rms
BW = 12 kHz to 20 MHz
CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4
80
fs rms
BW = 12 kHz to 20 MHz
CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16
215
fs rms
Calculated from SNR of ADC method;
DCC not used for even divides
CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5
245
fs rms
Calculated from SNR of ADC method; DCC on
LVDS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include
PLL and VCO; uses rising edge of clock signal
CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2;
VCO Divider Not Used
85
fs rms
BW = 12 kHz to 20 MHz
CLK = 1 GHz; LVDS = 200 MHz; Divider = 5
113
fs rms
BW = 12 kHz to 20 MHz
CLK = 1.6 GHz; LVDS = 100 MHz; Divider = 16
280
fs rms
Calculated from SNR of ADC method;
DCC not used for even divides
CMOS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include
PLL and VCO; uses rising edge of clock signal
CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16
365
fs rms
Calculated from SNR of ADC method;
DCC not used for even divides
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include
PLL and VCO; uses rising edge of clock signal
CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
210
fs rms
Calculated from SNR of ADC method
LVDS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include
PLL and VCO; uses rising edge of clock signal
CLK = 2.4 GHz; VCO DIV = 2; LVDS = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
285
fs rms
Calculated from SNR of ADC method
CMOS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include
PLL and VCO; uses rising edge of clock signal
CLK = 2.4 GHz; VCO DIV = 2; CMOS = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
350
fs rms
Calculated from SNR of ADC method
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
AD9517-2ABCPZ-RL7 功能描述:IC CLOCK GEN 2.2GHZ VCO 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
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