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參數(shù)資料
| 型號(hào)： | AD9517-2ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 44/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 2.2GHZ VCO 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:12 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.33GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤 |
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Data Sheet
AD9517-2
Rev. E | Page 49 of 80
LVPECL Outputs—OUT0 to OUT3
The LVPECL differential voltage (VOD) is selectable from ~400 mV
to ~960 mV (see Register 0x0F0[3:2] to Register 0x0F5[3:2]).
The LVPECL outputs have dedicated pins for power supply
(VS_LVPECL), allowing a separate power supply to be used.
VS_LVPECL can be from 2.5 V to 3.3 V.
The LVPECL output polarity can be set as noninverting or
inverting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring a
board layout change. Each LVPECL output can be powered
down or powered up as needed. Because of the architecture of
the LVPECL output stages, there is the possibility of electrical
overstress and breakdown under certain power-down conditions.
For this reason, the LVPECL outputs have several power-down
modes. This includes a safe power-down mode that continues
to protect the output devices while powered down, although it
consumes somewhat more power than a total power-down. If
the LVPECL output pins are terminated, it is best to select the
safe power-down mode. If the pins are left floating (i.e., not
connected), total power-down mode is fine.
GND
3.3V
OUT
06
42
6-
0
33
Figure 59. LVPECL Output Simplified Equivalent Circuit
LVDS/CMOS Outputs—OUT4 to OUT7
OUT4 to OUT7 can be configured as either an LVDS
differential output or as a pair of CMOS single-ended outputs.
The LVDS outputs allow for selectable output current from
~1.75 mA to ~7 mA.
The LVDS output polarity can be set as noninverting or
inverting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring a
board layout change. Each LVDS output can be powered down
if not needed to save power.
OUT4 to OUT7 can also be CMOS outputs. Each LVDS output
can be configured to be two CMOS outputs. This provides for
up to eight CMOS outputs: OUT4A, OUT4B, OUT5A, OUT5B,
OUT6A, OUT6B, OUT7A, and OUT7B. When an output is
configured as CMOS, CMOS Output A is automatically turned on.
CMOS Output B can be turned on or off independently. The
relative polarity of the CMOS outputs can also be selected for
any combination of inverting and noninverting (see Table 57,
Register 0x140[7:5], Register 0x141[7:5], Register 0x142[7:5],
and Register 0x143[7:5]).
OUT
3.5mA
06
42
6-
0
34
Figure 60. LVDS Output Simplified Equivalent Circuit with
3.5 mA Typical Current Source
Each LVDS/CMOS output can be powered-down as needed to
save power. The CMOS output power-down is controlled by the
same bit that controls the LVDS power-down for that output.
This power-down control affects both CMOS Output A and
CMOS Output B. However, when CMOS Output A is powered up,
CMOS Output B can be powered on or off separately.
OUT
VS
06
42
6-
0
35
Figure 61. CMOS Equivalent Output Circuit
RESET MODES
The AD9517 has several ways to force the chip into a reset
condition that restores all registers to their default values and
makes these settings active.
Power-On Reset—Start-Up Conditions When VS Is
Applied
A power-on reset (POR) is issued when the VS power supply is
turned on. This initializes the chip to the power-on conditions
that are determined by the default register settings. These are
indicated in the Default Value (Hex) column of Table 52. At
power-on, the AD9517 also executes a sync operation, which
brings the outputs into phase alignment according to the default
settings.
Asynchronous Reset via the RESET Pin
An asynchronous hard reset is executed by momentarily pulling
RESET low. A reset restores the chip registers to the default settings.
Soft Reset via Register 0x00[2]
A soft reset is executed by writing Register 0x000[2] and
Register 0x000[5] = 1b. This bit is not self-clearing; it must be
cleared by writing Register 0x000[2] and Register 0x000[5] = 0b to
reset it and complete the soft reset operation. A soft reset restores
the default values to the internal registers. The soft reset bit does
not require an update registers command (Register 0x232) to be
issued.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9517-2ABCPZ-RL7 | 功能描述:IC CLOCK GEN 2.2GHZ VCO 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9517-2BCPZ | 制造商:Analog Devices 功能描述:Clock Generator 48-Pin LFCSP EP Tray |
| AD9517-2BCPZ-REEL7 | 制造商:Analog Devices 功能描述: |
| AD9517-2BCPZ-TR | 制造商:Analog Devices 功能描述:OUPUT CLOCK GENERATOR WITH 2.2HZ VCO - Tape and Reel |
| AD9517-3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Output Clock Generator with Integrated 2.0 GHz VCO |
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