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參數(shù)資料
| 型號： | AD9517-4ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 71/80頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 1.8GHZ VCO 48LFCSP |
| 設計資源： | High Performance, Dual Channel IF Sampling Receiver (CN0140) |
| 標準包裝： | 1 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:12 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤 |
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Data Sheet
AD9517-4
Rev. E | Page 73 of 80
Reg.
Addr.
(Hex)
Bits
Name
Description
0x197
4
Divider 1 start high
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
[3:0]
Divider 1 phase offset
Phase offset (default = 0x0).
0x198
1
Divider 1 direct to output
Connects OUT2 and OUT3 to Divider 2 or directly to VCO or CLK.
0: OUT2 and OUT3 are connected to Divider 1 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT2 and OUT3.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT2 and OUT3.
If Register 0x1E1[1:0] = 01b, there is no effect.
0
Divider 1 DCCOFF
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Table 59. LVDS/CMOS Channel Dividers
Reg.
Addr.
(Hex)
Bits
Name
Description
0x199
[7:4]
Low Cycles Divider 2.1
Number of clock cycles (minus 1) of 2.1 divider input during which 2.1 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
[3:0]
High Cycles Divider 2.1
Number of clock cycles (minus 1) of 2.1 divider input during which 2.1 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
0x19A
[7:4]
Phase Offset Divider 2.2
Refer to LVDS/CMOS channel divider function description (default = 0x0).
[3:0]
Phase Offset Divider 2.1
Refer to LVDS/CMOS channel divider function description (default = 0x0).
0x19B
[7:4]
Low Cycles Divider 2.2
Number of clock cycles (minus 1) of 2.2 divider input during which 2.2 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
[3:0]
High Cycles Divider 2.2
Number of clock cycles (minus 1)of 2.2 divider input during which 2.2 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
0x19C
5
Bypass Divider 2.2
Bypasses (and powers down) 2.2 divider logic, routes clock to 2.2 output.
0: does not bypass (default).
1: bypasses.
4
Bypass Divider 2.1
Bypasses (and powers down) 2.1 divider logic, routes clock to 2.1 output.
0: does not bypass (default).
1: bypasses.
3
Divider 2 nosync
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
2
Divider 2 force high
Forces Divider 2 output high. Requires that nosync also be set.
0: forces low (default).
1: forces high.
1
Start High Divider 2.2
Divider 2.2 start high/low.
0: starts low (default).
1: starts high.
0
Start High Divider 2.1
Divider 2.1 start high/low.
0: starts low (default).
1: starts high.
0x19D
0
Divider 2 DCCOFF
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
0x19E
[7:4]
Low Cycles Divider 3.1
Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
[3:0]
High Cycles Divider 3.1
Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9517-4ABCPZ | 制造商:Analog Devices 功能描述:CLOCK GENERATOR 1.8GHZ LFCSP |
| AD9517-4ABCPZ-RL7 | 功能描述:IC CLOCK GEN 1.8GHZ VCO 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9517-4APCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Output Clock Generator with Integrated 1.6 GHz VCO |
| AD9517-4BCPZ | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:IC CLOCK GENERATOR 1.8GHZ LFCSP-48 制造商:Analog Devices 功能描述:IC, CLOCK GENERATOR, 1.8GHZ, LFCSP-48, Clock IC Type:Clock Generator, Frequency: |
| AD9517-4BCPZ-REEL7 | 制造商:Analog Devices 功能描述: |
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