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參數(shù)資料
| 型號(hào)： | AD9600ABCPZ-150 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 36/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 150MSPS 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 150M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 890mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個(gè)單端，單極；2 個(gè)差分，單極 |
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AD9600
Rev. B | Page 41 of 72
MEMORY MAP
All address and bit locations that are not included in Table 22 are currently not supported for this device.
Table 22. Memory Map Registers
Addr
(Hex)
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
Chip Configuration Registers
0x00
SPI Port
Configuration
(Global)
0
LSB first
Soft reset
1
Soft reset
LSB first
0
0x18
The nibbles
are mirrored
so that LSB- or
MSB-first mode
is set correctly,
regardless of
shift mode.
0x01
Chip ID
(Global)
8-bit Chip ID [7:0]
(AD9600 = 0x21)
(default)
0x21
Read
only
Read only.
0x02
Chip Grade
(Global)
Open
Speed grade ID
00 = 150 MSPS
01 = 125 MSPS
10 = 105 MSPS
11 = 80 MSPS
Open
Read
only
Speed grade
ID used to
differentiate
devices.
Channel Index and Transfer Registers
0x05
Channel Index
Open
Data
Channel B
(default)
Data
Channel A
(default)
0x03
Bits are set
to determine
which on-chip
device receives
the next write
command;
applies to local
registers.
0xFF
Transfer
Open
Transfer
0x00
Synchronously
transfers data
from the
master shift
register to the
slave.
ADC Functions Registers
0x08
Power Modes
Open
External
power-
down pin
function
(global)
0 = power-
down
1 = standby
Open
Internal power-down
mode (local)
00 = normal operation
01 = full power-down
10 = standby
11 = normal operation
0x00
Determines
various generic
modes of chip
operation.
0x09
Global Clock
(Global)
Open
Duty cycle
stabilizer
(default)
0x01
0x0B
Clock Divide
(Global)
Open
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
0x00
Clock divide
values other
than 000
automatically
cause the duty
cycle stabilizer
to become
active.
0x0D
Test Mode
(Local)
Open
Reset PN23
gen
Reset
PN9 gen
Open
Output test mode
000 = off (default)
001 = midscale short
010 = positive FS
011 = negative FS
100 = alternating checkerboard
101 = PN 23 sequence
110 = PN 9 sequence
111 = one/zero word toggle
0x00
When this
register is set,
the test data is
placed on the
output pins in
place of normal
data.
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