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| 型號： | AD9608-125EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/40頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL AD9608-125 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 串行 |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9608 |
| 已供物品： | 板 |
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AD9608
Rev. 0 | Page 23 of 40
THEORY OF OPERATION
The AD9608 dual ADC design can be used for diversity reception
of signals, where the ADCs are operating identically on the same
carrier but from two separate antennae. The ADCs can also be
operated with independent analog inputs. The user can sample
any fS/2 frequency segment from dc to 200 MHz, using appropriate
low-pass or band-pass filtering at the ADC inputs with little loss
in ADC performance. Operation to 300 MHz analog input is
permitted but occurs at the expense of increased ADC noise
and distortion.
In nondiversity applications, the AD9608 can be used as a base-
band or direct downconversion receiver, where one ADC is
used for I input data and the other is used for Q input data.
Synchronization capability is provided to allow synchronized
timing between multiple channels or multiple devices.
Programming and control of the AD9608 is accomplished using
a 3-bit SPI-compatible serial interface.
ADC ARCHITECTURE
The AD9608 architecture consists of a multistage, pipelined ADC.
Each stage provides sufficient overlap to correct for flash errors in
the preceding stage. The quantized outputs from each stage are
combined into a final 10-bit result in the digital correction logic.
The pipelined architecture permits the first stage to operate with
a new input sample while the remaining stages operate with
preceding samples. Sampling occurs on the rising edge of
the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage consists of a flash ADC.
The output staging block aligns the data, corrects errors, and
passes the data to the CMOS/LVDS output buffers. The output
buffers are powered from a separate (DRVDD) supply, allowing
digital output noise to be separated from the analog core. During
power-down, the output buffers go into a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9608 is a differential switched-
capacitor circuit designed for processing differential input
signals. This circuit can support a wide common-mode range
while maintaining excellent performance. By using an input
common-mode voltage of midsupply, users can minimize
signal-dependent errors and achieve optimum performance.
SS
CPAR
CSAMPLE
CPAR
VIN–x
H
SS
H
VIN+x
H
0997
7-
049
Figure 42. Switched-Capacitor Input Circuit
The clock signal alternately switches the input circuit between
sample-and-hold mode (see Figure 42). When the input circuit
is switched to sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can help
reduce the peak transient current injected from the output stage
of the driving source. In addition, low Q inductors or ferrite beads
can be placed on each leg of the input to reduce high differential
capacitance at the analog inputs and, therefore, achieve the
maximum bandwidth of the ADC. Such use of low Q inductors
or ferrite beads is required when driving the converter front end
at high IF frequencies. Either a shunt capacitor or two single-ended
capacitors can be placed on the inputs to provide a matching
passive network. This ultimately creates a low-pass filter at the
input to limit unwanted broadband noise. See the AN-742
Application Note, the AN-827 Application Note, and the Analog
Dialogue article “Transformer-Coupled Front-End for Wideband
A/D Converters” (Volume 39, April 2005) for more information.
In general, the precise values depend on the application.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9608-125EBZ | 制造商:Analog Devices 功能描述:AD9608, ADC, SPI, EVALUATION BOARD |
| AD9608BCPZ-105 | 功能描述:IC ADC DUAL 10BIT 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD9608BCPZ-125 | 功能描述:IC ADC DUAL 10BIT 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD9608BCPZRL7-105 | 功能描述:IC ADC 10BIT 105MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD9608BCPZRL7-125 | 功能描述:IC ADC 10BIT 125MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
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