參數(shù)資料
型號(hào): AD9627ABCPZ-105
廠商: Analog Devices Inc
文件頁(yè)數(shù): 29/76頁(yè)
文件大?。?/td> 0K
描述: IC ADC 12BIT 105MSPS 64LFCSP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 12
采樣率(每秒): 105M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 650mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤(pán)
輸入數(shù)目和類(lèi)型: 4 個(gè)單端,單極;2 個(gè)差分,單極
AD9627
Rev. B | Page 35 of 76
Increment Gain (IG) and Decrement Gain (DG)
The increment gain and decrement gain indicators are intended
to be used together to provide information to enable external
gain control. The decrement gain indicator works in conjunction
with the coarse upper threshold bits, asserting when the input
magnitude is greater than the 3-bit value in the coarse upper
threshold register (Address 0x105). The increment gain indicator,
similarly, corresponds to the fine lower threshold bits, except
that it is asserted only if the input magnitude is less than the
value programmed in the fine lower threshold register after the
dwell time elapses. The dwell time is set by the 16-bit dwell time
value located at Address 0x10A and Address 0x10B and is set in
units of ADC input clock cycles ranging from 1 to 65,535. The
fine lower threshold register is a 13-bit register that is compared
with the magnitude at the output of the ADC. This comparison
is subject to the ADC clock latency but allows a finer, more
accurate comparison. The fine upper threshold magnitude is
defined by the following equation:
dBFS = 20 log(Threshold Magnitude/213)
The decrement gain output works from the ADC fast detect
output pins, providing a fast indication of potential overrange
conditions. The increment gain uses the comparison at the
output of the ADC, requiring the input magnitude to remain
below an accurate, programmable level for a predefined period
before signaling external circuitry to increase the gain.
The operation of the increment gain output and the decrement
gain output is shown in Figure 67.
UPPER THRESHOLD (COARSE OR FINE)
FINE LOWER THRESHOLD
IG
DG
F_LT
C_UT OR F_UT*
DWELL TIME
TIMER RESET BY
RISE ABOVE F_LT
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE F_LT
NOTE: OUTPUTS FOLLOW THE INSTANTANEOUS SIGNAL LEVEL AND NOT THE ENVELOPE BUT ARE GUARANTEED ACTIVE FOR A MINIMUM OF 2 ADC CLOCK CYCLES.
*C_UT AND F_UT DIFFER ONLY IN ACCURACY AND LATENCY.
DWELL TIME
0
65
71
-0
67
Figure 67. Threshold Settings for C_UT, F_UT, IG, DG, and F_LT
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