參數(shù)資料
型號(hào)： AD9627ABCPZ-105
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 31/76頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 105MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 105M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 650mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤(pán)
輸入數(shù)目和類(lèi)型： 4 個(gè)單端，單極；2 個(gè)差分，單極
AD9627
Rev. B | Page 37 of 76
Figure 69 illustrates the rms magnitude monitoring logic.
SIGNAL MONITOR
HOLDING
REGISTER (SMR)
ACCUMULATOR
TO
MEMORY
MAP/SPORT
FROM
MEMORY
MAP
FROM
INPUT
PORTS
LOAD
CLEAR
LOAD
IS COUNT = 1?
DOWN
COUNTER
SIGNAL MONITOR
PERIOD REGISTER
06
57
1-
06
9
Figure 69. ADC Input RMS Magnitude Monitoring Block Diagram
For rms magnitude mode, the value in the signal monitoring result
(SMR) register is a 20-bit fixed-point number. The following
equation can be used to determine the rms magnitude in dBFS
from the MAG value in the register. Note that if the signal monitor
period (SMP) is a power of 2, the second term in the equation
becomes 0.
RMS Magnitude = 20 log
)
(
log
ceil
20
2
log
10
2
SMP
MAG
For ms magnitude mode, the value in the SMR is a 20-bit fixed-
point number. The following equation can be used to determine
the ms magnitude in dBFS from the MAG value in the register.
Note that if the SMP is a power of 2, the second term in the
equation becomes 0.
MS Magnitude = 10 log
)
(
log
ceil
20
2
log
10
2
SMP
MAG
THRESHOLD CROSSING MODE
In the threshold crossing mode of operation, the magnitude of
the input port signal is monitored over a programmable time
period (given by SMPR) to count the number of times it crosses
a certain programmable threshold value. This mode is set by
programming Logic 1x (where x is a don’t care bit) in the signal
monitor mode bits of the signal monitor control register or by
setting the threshold crossing output enable bit in the signal
monitor SPORT control register. Before activating this mode,
the user needs to program the 24-bit SMPR and the 13-bit
upper threshold register for each individual input port. The
same upper threshold register is used for both signal monitoring
and gain control (see the ADC Overrange and Gain Control
section).
After entering this mode, the value in the SMPR is loaded into
a monitor period timer, and the countdown is started. The magni-
tude of the input signal is compared with the upper threshold
register (programmed previously) on each input clock cycle.
If the input signal has a magnitude greater than the upper
threshold register, the internal count register is incremented by 1.
The initial value of the internal count register is set to 0. This
comparison and incrementing of the internal count register
continues until the monitor period timer reaches a count of 1.
When the monitor period timer reaches a count of 1, the value
in the internal count register is transferred to the signal monitor
holding register, which can be read through the SPI port or output
through the SPORT serial port.
The monitor period timer is reloaded with the value in the SMPR
register, and the countdown is restarted. The internal count
register is also cleared to a value of 0. Figure 70 illustrates the
threshold crossing logic. The value in the SMR register is the
number of samples that have a magnitude greater than the
threshold register.
SIGNAL MONITOR
HOLDING
REGISTER (SMR)
COMPARE
A > B
UPPER
THRESHOLD
REGISTER
COMPARE
A > B
TO
MEMORY
MAP/SPORT
FROM
MEMORY
MAP
FROM
MEMORY
MAP
FROM
INPUT
PORTS
LOAD
CLEAR
LOAD
IS COUNT = 1?
DOWN
COUNTER
SIGNAL MONITOR
PERIOD REGISTER
B
A
0
657
1-
0
70
Figure 70. ADC Input Threshold Crossing Block Diagram
ADDITIONAL CONTROL BITS
For additional flexibility in the signal monitoring process, two
control bits are provided in the signal monitor control register.
They are the signal monitor enable bit and the complex power
calculation mode enable bit.
Signal Monitor Enable Bit
The signal monitor enable bit, located in Bit 0 of Register 0x112,
enables operation of the signal monitor block. If the signal monitor
function is not needed in a particular application, this bit should
be cleared (default) to conserve power.
Complex Power Calculation Mode Enable Bit
When this bit is set, the part assumes that Channel A is digitizing
the I data and Channel B is digitizing the Q data for a complex
input signal (or vice versa). In this mode, the power reported is
equal to
2
Q
I
This result is presented in the Signal Monitor DC Value Channel A
register if the signal monitor mode bits are set to 00. The Signal
Monitor DC Value Channel B register continues to compute the
Channel B value.
DC CORRECTION
Because the dc offset of the ADC may be significantly larger
than the signal being measured, a dc correction circuit is included
to null the dc offset before measuring the power. The dc correction
circuit can also be switched into the main signal path, but this
may not be appropriate if the ADC is digitizing a time-varying
signal with significant dc content, such as GSM.
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