參數(shù)資料
型號: AD9640-105EBZ
廠商: Analog Devices Inc
文件頁數(shù): 9/52頁
文件大小: 0K
描述: ADC 14BIT 105MSPS DUAL 64-LFCSP
設(shè)計資源: Interfacing ADL5534 to AD9640 High Speed ADC (CN0049)
AD9640 Eval Brd Family Gerber Files
AD9640 Eval Brd BOM
AD9640 Eval Brd Schematic
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 2
位數(shù): 14
采樣率(每秒): 105M
數(shù)據(jù)接口: 串行
輸入范圍: 2 Vpp
在以下條件下的電源(標(biāo)準(zhǔn)): 730mW @ 105MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9640
已供物品:
AD9640
Rev. B | Page 17 of 52
PIN 1
INDICATOR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D7
+
D8–
D8
+
DRG
ND
DR
VD
D
D9–
D9
+
DV
D
D10–
D10+
D1
1
D1
1
+
D12–
D12+
(
M
S
B
)
+
(
M
S
B
)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DRG
ND
D0+
(
L
S
B
)
D0–
(
L
S
B
)
FD
3
+
FD
3
FD
2
+
FD
2
DV
DD
FD
1
+
FD
1
FD
0
+
FD
0
SY
N
C
CS
B
CL
K–
CL
K+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DRVDD
D1–
D1+
D2–
D2+
D3–
D3+
D4–
D4+
DCO–
DCO+
D5–
D5+
D6–
D6+
D7–
SCLK/DFS
SDIO/DCS
AVDD
VIN+B
VIN–B
RBIAS
CML
SENSE
VREF
VIN–A
VIN+A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
D13–
D13
AD9640
PARALLEL LVDS
TOP VIEW
(Not to Scale)
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
06
54
7-
0
03
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES
THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 7. Pin Configuration, LFCSP LVDS (Top View)
Table 12. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No.
Mnemonic
Type
Function
ADC Power Supplies
20, 64
DRGND
Ground
Digital Output Ground.
1, 21
DRVDD
Supply
Digital Output Driver Supply (1.8 V to 3.3 V).
24, 57
DVDD
Supply
Digital Power Supply (1.8 V Nominal).
36, 45, 46
AVDD
Supply
Analog Power Supply (1.8 V Nominal).
0
AGND,
Exposed Pad
Ground
The exposed thermal pad on the bottom of the package provides the analog ground for the
part. This exposed pad must be connected to ground for proper operation.
ADC Analog
37
VIN+A
Input
Differential Analog Input Pin (+) for Channel A.
38
VINA
Input
Differential Analog Input Pin () for Channel A.
44
VIN+B
Input
Differential Analog Input Pin (+) for Channel B.
43
VINB
Input
Differential Analog Input Pin () for Channel B.
39
VREF
Input/Output
Voltage Reference Input/Output.
40
SENSE
Input
Voltage Reference Mode Select. See Table 14 for details.
42
RBIAS
Input/Output
External Reference Bias Resistor.
41
CML
Output
Common-Mode Level Bias Output for Analog Inputs.
49
CLK+
Input
ADC Clock Input—True.
50
CLK
Input
ADC Clock Input—Complement.
ADC Fast Detect Outputs
54
FD0+
Output
Channel A/Channel B LVDS Fast Detect Indicator 0—True. See Table 18 for details.
53
FD0
Output
Channel A/Channel B LVDS Fast Detect Indicator 0—Complement. See Table 18 for details.
56
FD1+
Output
Channel A/Channel B LVDS Fast Detect Indicator 1—True. See Table 18 for details.
55
FD1
Output
Channel A/Channel B LVDS Fast Detect Indicator 1—Complement. See Table 18 for details.
59
FD2+
Output
Channel A/Channel B LVDS Fast Detect Indicator 2—True. See Table 18 for details.
58
FD2
Output
Channel A/Channel B LVDS Fast Detect Indicator 2—Complement. See Table 18 for details.
61
FD3+
Output
Channel A/Channel B LVDS Fast Detect Indicator 3—True. See Table 18 for details.
60
FD3
Output
Channel A/Channel B LVDS Fast Detect Indicator 3—Complement. See Table 18 for details.
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